Revert "spl: imx6: Let spl_boot_device return USDHC1 or USDHC2"

[oweals/u-boot.git] / arch / arm / mach-imx / mx7 / clock.c

diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 2cfde46a5532d29dda738fd8bfa4d0740142b34c..0e08cabb7ad07ac858aba02ba39349600b3a068c 100644 (file)
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
  *
  * Author:
  *     Peng Fan <Peng.Fan@freescale.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -20,13 +19,13 @@ struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
                                         ANATOP_BASE_ADDR;
 struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 int get_clocks(void)
 {
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
        gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
@@ -54,7 +53,7 @@ static u32 get_ipg_clk(void)
 
 u32 imx_get_uartclk(void)
 {
-       return get_root_clk(UART1_CLK_ROOT);
+       return get_root_clk(UART_CLK_ROOT);
 }
 
 u32 imx_get_fecclk(void)
@@ -966,15 +965,15 @@ int set_clk_enet(enum enet_freq type)
        clock_enable(CCGR_ENET2, 0);
 
        switch (type) {
-       case ENET_125MHz:
+       case ENET_125MHZ:
                enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
                enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
                break;
-       case ENET_50MHz:
+       case ENET_50MHZ:
                enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
                enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
                break;
-       case ENET_25MHz:
+       case ENET_25MHZ:
                enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
                enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
                break;
@@ -1075,7 +1074,7 @@ void clock_init(void)
        }
 }
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 void hab_caam_clock_enable(unsigned char enable)
 {
        if (enable)
@@ -1096,6 +1095,7 @@ void epdc_clock_disable(void)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */
@@ -1131,3 +1131,4 @@ U_BOOT_CMD(
        "display clocks",
        ""
 );
+#endif