Merge git://git.denx.de/u-boot-fsl-qoriq

[oweals/u-boot.git] / arch / arm / mach-imx / mx6 / soc.c

diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 760745656feb9fa80f5d27d39e21669bc8529953..ad72c125117dd5cd7cade5a07d12934dfc5f8f48 100644 (file)
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -13,6 +13,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/bootm.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/dma.h>
 #include <asm/mach-imx/hab.h>
@@ -114,6 +115,12 @@ u32 get_cpu_rev(void)
 #define OCOTP_CFG3_SPEED_528MHZ 1
 #define OCOTP_CFG3_SPEED_696MHZ 2
 
+/*
+ * For i.MX6ULL
+ */
+#define OCOTP_CFG3_SPEED_792MHZ 2
+#define OCOTP_CFG3_SPEED_900MHZ 3
+
 u32 get_cpu_speed_grade_hz(void)
 {
        struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -126,7 +133,7 @@ u32 get_cpu_speed_grade_hz(void)
        val >>= OCOTP_CFG3_SPEED_SHIFT;
        val &= 0x3;
 
-       if (is_mx6ul() || is_mx6ull()) {
+       if (is_mx6ul()) {
                if (val == OCOTP_CFG3_SPEED_528MHZ)
                        return 528000000;
                else if (val == OCOTP_CFG3_SPEED_696MHZ)
@@ -135,6 +142,17 @@ u32 get_cpu_speed_grade_hz(void)
                        return 0;
        }
 
+       if (is_mx6ull()) {
+               if (val == OCOTP_CFG3_SPEED_528MHZ)
+                       return 528000000;
+               else if (val == OCOTP_CFG3_SPEED_792MHZ)
+                       return 792000000;
+               else if (val == OCOTP_CFG3_SPEED_900MHZ)
+                       return 900000000;
+               else
+                       return 0;
+       }
+
        switch (val) {
        /* Valid for IMX6DQ */
        case OCOTP_CFG3_SPEED_1P2GHZ:
@@ -234,6 +252,10 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
        u32 val, step, old, reg = readl(&anatop->reg_core);
        u8 shift;
 
+       /* No LDO_SOC/PU/ARM */
+       if (is_mx6sll())
+               return 0;
+
        if (mv < 725)
                val = 0x00;     /* Power gated off */
        else if (mv > 1450)
@@ -293,7 +315,7 @@ static void clear_mmdc_ch_mask(void)
        reg = readl(&mxc_ccm->ccdr);
 
        /* Clear MMDC channel mask */
-       if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
+       if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
                reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
        else
                reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
@@ -344,20 +366,10 @@ static void init_bandgap(void)
        }
 }
 
-#ifdef CONFIG_MX6SL
-static void set_preclk_from_osc(void)
-{
-       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-       u32 reg;
-
-       reg = readl(&mxc_ccm->cscmr1);
-       reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
-       writel(reg, &mxc_ccm->cscmr1);
-}
-#endif
-
 int arch_cpu_init(void)
 {
+       struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
        init_aips();
 
        /* Need to clear MMDC_CHx_MASK to make warm reset work. */
@@ -421,12 +433,14 @@ int arch_cpu_init(void)
        }
 
        /* Set perclk to source from OSC 24MHz */
-#if defined(CONFIG_MX6SL)
-       set_preclk_from_osc();
-#endif
+       if (is_mx6sl())
+               setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
 
        imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 
+       if (is_mx6sx())
+               setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
+
        init_src();
 
        return 0;
@@ -495,6 +509,10 @@ uint mmc_get_env_part(struct mmc *mmc)
 
 int board_postclk_init(void)
 {
+       /* NO LDO SOC on i.MX6SLL */
+       if (is_mx6sll())
+               return 0;
+
        set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
 
        return 0;
@@ -534,6 +552,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * cfg_val will be used for
  * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
@@ -560,6 +579,7 @@ const struct boot_mode soc_boot_modes[] = {
        {"esdhc4",      MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
        {NULL,          0},
 };
+#endif
 
 void reset_misc(void)
 {
@@ -576,7 +596,7 @@ void s_init(void)
        u32 mask528;
        u32 reg, periph1, periph2;
 
-       if (is_mx6sx() || is_mx6ul() || is_mx6ull())
+       if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
                return;
 
        /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
@@ -664,6 +684,23 @@ void imx_setup_hdmi(void)
 }
 #endif
 
+void gpr_init(void)
+{
+       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+       /* enable AXI cache for VDOA/VPU/IPU */
+       writel(0xF00000CF, &iomux->gpr[4]);
+       if (is_mx6dqp()) {
+               /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+               writel(0x77177717, &iomux->gpr[6]);
+               writel(0x77177717, &iomux->gpr[7]);
+       } else {
+               /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+               writel(0x007F007F, &iomux->gpr[6]);
+               writel(0x007F007F, &iomux->gpr[7]);
+       }
+}
+
 #ifdef CONFIG_IMX_BOOTAUX
 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
 {