imx8mm: Update CPU speed grading

[oweals/u-boot.git] / arch / arm / mach-imx / mx5 / clock.c

diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c
index 284f6d4cde3d99b05e105b812a799f7187787551..2fabdd2eae8ed8c93ed1d60bb4832eeac7cc35a3 100644 (file)
--- a/arch/arm/mach-imx/mx5/clock.c
+++ b/arch/arm/mach-imx/mx5/clock.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2007
  * Sascha Hauer, Pengutronix
  *
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -839,6 +838,31 @@ static int config_ddr_clk(u32 emi_clk)
        return 0;
 }
 
+#ifdef CONFIG_MX53
+static int config_ldb_clk(u32 ref, u32 freq)
+{
+       int ret = 0;
+       struct pll_param pll_param;
+
+       memset(&pll_param, 0, sizeof(struct pll_param));
+
+       ret = calc_pll_params(ref, freq, &pll_param);
+       if (ret != 0) {
+               printf("Error:Can't find pll parameters: %d\n",
+                       ret);
+               return ret;
+       }
+
+       return config_pll_clk(PLL4_CLOCK, &pll_param);
+}
+#else
+static int config_ldb_clk(u32 ref, u32 freq)
+{
+       /* Platform not supported */
+       return -EINVAL;
+}
+#endif
+
 /*
  * This function assumes the expected core clock has to be changed by
  * modifying the PLL. This is NOT true always but for most of the times,
@@ -880,6 +904,10 @@ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
                if (config_nfc_clk(freq))
                        return -EINVAL;
                break;
+       case MXC_LDB_CLK:
+               if (config_ldb_clk(ref, freq))
+                       return -EINVAL;
+               break;
        default:
                printf("Warning:Unsupported or invalid clock type\n");
        }