zynq: Kconfig: extend the bootstrap malloc() pool

[oweals/u-boot.git] / arch / arm / mach-imx / ddrmc-vf610.c

diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c
index 7cc8f5d2c0c7114e67e56bbdb3ed47c42ee7ead9..fa948f78120c58fcb2a2f468990c4600d76520c8 100644 (file)
--- a/arch/arm/mach-imx/ddrmc-vf610.c
+++ b/arch/arm/mach-imx/ddrmc-vf610.c
@@ -190,7 +190,6 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
                   DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
        writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
                   DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
-       writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
 
        writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
 
@@ -233,6 +232,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
        /* all inits done, start the DDR controller */
        writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
 
-       while (!(readl(&ddrmr->cr[80]) && 0x100))
+       while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
                udelay(10);
+       writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
 }