+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <bootm.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
+#include <asm/mach-imx/boot_mode.h>
#include <imx_thermal.h>
#include <ipu_pixfmt.h>
#include <thermal.h>
return "WDOG4";
case 0x00200:
return "TEMPSENSE";
-#elif defined(CONFIG_MX8M)
+#elif defined(CONFIG_IMX8M)
case 0x00100:
return "WDOG2";
case 0x00200:
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
- case MXC_CPU_MX8MQ:
- return "8MQ"; /* Quad-core version of the mx8m */
+ case MXC_CPU_IMX8MQ:
+ return "8MQ"; /* Quad-core version of the imx8m */
case MXC_CPU_MX7S:
return "7S"; /* Single-core version of the mx7 */
case MXC_CPU_MX7D:
}
#endif
-#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
+#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
u32 get_ahb_clk(void)
{
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
#endif
}
-#ifndef CONFIG_MX8M
+#ifndef CONFIG_IMX8M
void set_chipselect_size(int const cs_size)
{
unsigned int reg;
}
#endif
-#if defined(CONFIG_MX7)
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
/*
* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
* defines a 2-bit SPEED_GRADING
*/
#define OCOTP_TESTER3_SPEED_SHIFT 8
-#define OCOTP_TESTER3_SPEED_800MHZ 0
-#define OCOTP_TESTER3_SPEED_500MHZ 1
-#define OCOTP_TESTER3_SPEED_1GHZ 2
-#define OCOTP_TESTER3_SPEED_1P2GHZ 3
+enum cpu_speed {
+ OCOTP_TESTER3_SPEED_GRADE0,
+ OCOTP_TESTER3_SPEED_GRADE1,
+ OCOTP_TESTER3_SPEED_GRADE2,
+ OCOTP_TESTER3_SPEED_GRADE3,
+};
u32 get_cpu_speed_grade_hz(void)
{
val &= 0x3;
switch(val) {
- case OCOTP_TESTER3_SPEED_800MHZ:
+ case OCOTP_TESTER3_SPEED_GRADE0:
return 800000000;
- case OCOTP_TESTER3_SPEED_500MHZ:
- return 500000000;
- case OCOTP_TESTER3_SPEED_1GHZ:
- return 1000000000;
- case OCOTP_TESTER3_SPEED_1P2GHZ:
- return 1200000000;
+ case OCOTP_TESTER3_SPEED_GRADE1:
+ return is_mx7() ? 500000000 : 1000000000;
+ case OCOTP_TESTER3_SPEED_GRADE2:
+ return is_mx7() ? 1000000000 : 1300000000;
+ case OCOTP_TESTER3_SPEED_GRADE3:
+ return is_mx7() ? 1200000000 : 1500000000;
}
+
return 0;
}
}
#endif
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
+enum boot_device get_boot_device(void)
+{
+ struct bootrom_sw_info **p =
+ (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
+
+ enum boot_device boot_dev = SD1_BOOT;
+ u8 boot_type = (*p)->boot_dev_type;
+ u8 boot_instance = (*p)->boot_dev_instance;
+
+ switch (boot_type) {
+ case BOOT_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BOOT_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BOOT_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BOOT_TYPE_QSPI:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BOOT_TYPE_WEIM:
+ boot_dev = WEIM_NOR_BOOT;
+ break;
+ case BOOT_TYPE_SPINOR:
+ boot_dev = SPI_NOR_BOOT;
+ break;
+#ifdef CONFIG_IMX8M
+ case BOOT_TYPE_USB:
+ boot_dev = USB_BOOT;
+ break;
+#endif
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
+#endif
+
#ifdef CONFIG_NXP_BOARD_REVISION
int nxp_board_rev(void)
{