Merge tag 'uniphier-v2019.07' of git://git.denx.de/u-boot-uniphier

[oweals/u-boot.git] / arch / arm / mach-imx / cpu.c

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 52dbafb50cec8b3e5bc7a123fe595cd9632a2b15..6b83f926623366cda86b14a2ec1c855046ba491a 100644 (file)
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2007
  * Sascha Hauer, Pengutronix
  *
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <bootm.h>
@@ -16,6 +15,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <imx_thermal.h>
 #include <ipu_pixfmt.h>
 #include <thermal.h>
@@ -25,19 +25,27 @@
 #include <fsl_esdhc.h>
 #endif
 
-#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
 static u32 reset_cause = -1;
 
-static char *get_reset_cause(void)
+u32 get_imx_reset_cause(void)
 {
-       u32 cause;
        struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 
-       cause = readl(&src_regs->srsr);
-       writel(cause, &src_regs->srsr);
-       reset_cause = cause;
+       if (reset_cause == -1) {
+               reset_cause = readl(&src_regs->srsr);
+/* preserve the value for U-Boot proper */
+#if !defined(CONFIG_SPL_BUILD)
+               writel(reset_cause, &src_regs->srsr);
+#endif
+       }
+
+       return reset_cause;
+}
 
-       switch (cause) {
+#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
+static char *get_reset_cause(void)
+{
+       switch (get_imx_reset_cause()) {
        case 0x00001:
        case 0x00011:
                return "POR";
@@ -62,7 +70,7 @@ static char *get_reset_cause(void)
                return "WDOG4";
        case 0x00200:
                return "TEMPSENSE";
-#elif defined(CONFIG_MX8M)
+#elif defined(CONFIG_IMX8M)
        case 0x00100:
                return "WDOG2";
        case 0x00200:
@@ -77,11 +85,6 @@ static char *get_reset_cause(void)
                return "unknown reset";
        }
 }
-
-u32 get_imx_reset_cause(void)
-{
-       return reset_cause;
-}
 #endif
 
 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
@@ -142,8 +145,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
        switch (imxtype) {
-       case MXC_CPU_MX8MQ:
-               return "8MQ";   /* Quad-core version of the mx8m */
+       case MXC_CPU_IMX8MQ:
+               return "8MQ";   /* Quad-core version of the imx8m */
        case MXC_CPU_MX7S:
                return "7S";    /* Single-core version of the mx7 */
        case MXC_CPU_MX7D:
@@ -266,7 +269,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
+#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 u32 get_ahb_clk(void)
 {
        struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -300,7 +303,7 @@ void arch_preboot_os(void)
 #endif
 }
 
-#ifndef CONFIG_MX8M
+#ifndef CONFIG_IMX8M
 void set_chipselect_size(int const cs_size)
 {
        unsigned int reg;
@@ -333,16 +336,18 @@ void set_chipselect_size(int const cs_size)
 }
 #endif
 
-#if defined(CONFIG_MX7)
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
 /*
  * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  * defines a 2-bit SPEED_GRADING
  */
 #define OCOTP_TESTER3_SPEED_SHIFT      8
-#define OCOTP_TESTER3_SPEED_800MHZ     0
-#define OCOTP_TESTER3_SPEED_500MHZ     1
-#define OCOTP_TESTER3_SPEED_1GHZ       2
-#define OCOTP_TESTER3_SPEED_1P2GHZ     3
+enum cpu_speed {
+       OCOTP_TESTER3_SPEED_GRADE0,
+       OCOTP_TESTER3_SPEED_GRADE1,
+       OCOTP_TESTER3_SPEED_GRADE2,
+       OCOTP_TESTER3_SPEED_GRADE3,
+};
 
 u32 get_cpu_speed_grade_hz(void)
 {
@@ -357,15 +362,16 @@ u32 get_cpu_speed_grade_hz(void)
        val &= 0x3;
 
        switch(val) {
-       case OCOTP_TESTER3_SPEED_800MHZ:
+       case OCOTP_TESTER3_SPEED_GRADE0:
                return 800000000;
-       case OCOTP_TESTER3_SPEED_500MHZ:
-               return 500000000;
-       case OCOTP_TESTER3_SPEED_1GHZ:
-               return 1000000000;
-       case OCOTP_TESTER3_SPEED_1P2GHZ:
-               return 1200000000;
+       case OCOTP_TESTER3_SPEED_GRADE1:
+               return is_mx7() ? 500000000 : 1000000000;
+       case OCOTP_TESTER3_SPEED_GRADE2:
+               return is_mx7() ? 1000000000 : 1300000000;
+       case OCOTP_TESTER3_SPEED_GRADE3:
+               return is_mx7() ? 1200000000 : 1500000000;
        }
+
        return 0;
 }
 
@@ -406,6 +412,48 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 }
 #endif
 
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
+enum boot_device get_boot_device(void)
+{
+       struct bootrom_sw_info **p =
+               (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
+
+       enum boot_device boot_dev = SD1_BOOT;
+       u8 boot_type = (*p)->boot_dev_type;
+       u8 boot_instance = (*p)->boot_dev_instance;
+
+       switch (boot_type) {
+       case BOOT_TYPE_SD:
+               boot_dev = boot_instance + SD1_BOOT;
+               break;
+       case BOOT_TYPE_MMC:
+               boot_dev = boot_instance + MMC1_BOOT;
+               break;
+       case BOOT_TYPE_NAND:
+               boot_dev = NAND_BOOT;
+               break;
+       case BOOT_TYPE_QSPI:
+               boot_dev = QSPI_BOOT;
+               break;
+       case BOOT_TYPE_WEIM:
+               boot_dev = WEIM_NOR_BOOT;
+               break;
+       case BOOT_TYPE_SPINOR:
+               boot_dev = SPI_NOR_BOOT;
+               break;
+#ifdef CONFIG_IMX8M
+       case BOOT_TYPE_USB:
+               boot_dev = USB_BOOT;
+               break;
+#endif
+       default:
+               break;
+       }
+
+       return boot_dev;
+}
+#endif
+
 #ifdef CONFIG_NXP_BOARD_REVISION
 int nxp_board_rev(void)
 {