Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

[oweals/u-boot.git] / arch / arm / mach-imx / cache.c

diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index 82257f3280f2c9a46c71168ac939bd68960ce515..4fd2e434488e10360f3e2d8969a16dde6a56ac6d 100644 (file)
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <asm/armv7.h>
 #include <asm/pl310.h>
 #include <asm/io.h>
@@ -37,7 +38,7 @@ static void enable_ca7_smp(void)
        }
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
@@ -82,7 +83,7 @@ void v7_outer_cache_enable(void)
 {
        struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-       unsigned int val;
+       unsigned int val, cache_id;
 
 
        /*
@@ -112,22 +113,24 @@ void v7_outer_cache_enable(void)
 
        val = readl(&pl310->pl310_prefetch_ctrl);
 
-       /* Turn on the L2 I/D prefetch */
-       val |= 0x30000000;
+       /* Turn on the L2 I/D prefetch, double linefill */
+       /* Set prefetch offset with any value except 23 as per errata 765569 */
+       val |= 0x7000000f;
 
        /*
         * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
-        * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+        * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL/SX/DQP
+        * is r3p2.
         * But according to ARM PL310 errata: 752271
         * ID: 752271: Double linefill feature can cause data corruption
         * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
         * Workaround: The only workaround to this erratum is to disable the
         * double linefill feature. This is the default behavior.
         */
-
-#ifndef CONFIG_MX6Q
-       val |= 0x40800000;
-#endif
+       cache_id = readl(&pl310->pl310_cache_id);
+       if (((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310)
+           && ((cache_id & L2X0_CACHE_ID_RTL_MASK) < L2X0_CACHE_ID_RTL_R3P2))
+               val &= ~(1 << 30);
        writel(val, &pl310->pl310_prefetch_ctrl);
 
        val = readl(&pl310->pl310_power_ctrl);