int i;
struct clk_bit_info *info;
- if (proid_is_exynos5420() || proid_is_exynos5422())
+ if (proid_is_exynos542x())
info = exynos542x_bit_info;
else
info = exynos5_bit_info;
unsigned long clock_get_periph_rate(int peripheral)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5422())
+ if (proid_is_exynos542x())
return exynos542x_get_periph_rate(peripheral);
return exynos5_get_periph_rate(peripheral);
} else {
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5422())
+ if (proid_is_exynos542x())
return exynos542x_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else if (cpu_is_exynos4()) {
div -= 1;
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5422())
+ if (proid_is_exynos542x())
exynos5420_set_mmc_clk(dev_index, div);
else
exynos5_set_mmc_clk(dev_index, div);
int set_spi_clk(int periph_id, unsigned int rate)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5422())
+ if (proid_is_exynos542x())
return exynos5420_set_spi_clk(periph_id, rate);
return exynos5_set_spi_clk(periph_id, rate);
}