exynos: Add proid_is_exynos542x() for common 542x
[oweals/u-boot.git] / arch / arm / mach-exynos / clock.c
index 6a3cd44b5d3ea89e53bd9d72be85b3cf1080999d..2425a7286696fd340c378db9fc7888b92aa8dcda 100644 (file)
@@ -345,7 +345,7 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral)
        int i;
        struct clk_bit_info *info;
 
-       if (proid_is_exynos5420() || proid_is_exynos5422())
+       if (proid_is_exynos542x())
                info = exynos542x_bit_info;
        else
                info = exynos5_bit_info;
@@ -557,7 +557,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
 unsigned long clock_get_periph_rate(int peripheral)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420() || proid_is_exynos5422())
+               if (proid_is_exynos542x())
                        return exynos542x_get_periph_rate(peripheral);
                return exynos5_get_periph_rate(peripheral);
        } else {
@@ -1575,7 +1575,7 @@ static unsigned long exynos4_get_i2c_clk(void)
 unsigned long get_pll_clk(int pllreg)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420() || proid_is_exynos5422())
+               if (proid_is_exynos542x())
                        return exynos542x_get_pll_clk(pllreg);
                return exynos5_get_pll_clk(pllreg);
        } else if (cpu_is_exynos4()) {
@@ -1691,7 +1691,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
                div -= 1;
 
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420() || proid_is_exynos5422())
+               if (proid_is_exynos542x())
                        exynos5420_set_mmc_clk(dev_index, div);
                else
                        exynos5_set_mmc_clk(dev_index, div);
@@ -1739,7 +1739,7 @@ void set_mipi_clk(void)
 int set_spi_clk(int periph_id, unsigned int rate)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420() || proid_is_exynos5422())
+               if (proid_is_exynos542x())
                        return exynos5420_set_spi_clk(periph_id, rate);
                return exynos5_set_spi_clk(periph_id, rate);
        }