Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh

[oweals/u-boot.git] / arch / arm / mach-at91 / include / mach / sama5d2.h

diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index c85571c999eda4cc35da828e9a4fe63f5aceab3c..a4ec0aac619cb6d8a98a3750f7f332791d6b5a56 100644 (file)
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -10,11 +10,6 @@
 #ifndef __SAMA5D2_H
 #define __SAMA5D2_H
 
-/*
- * definitions to be used in other places
- */
-#define CONFIG_AT91FAMILY      /* It's a member of AT91 */
-
 /*
  * Peripheral identifiers/interrupts.
  */
@@ -106,6 +101,7 @@
 #define ATMEL_BASE_MPDDRC      0xf000c000
 #define ATMEL_BASE_XDMAC0      0xf0010000
 #define ATMEL_BASE_PMC         0xf0014000
+#define ATMEL_BASE_MATRIX0     0xf0018000
 #define ATMEL_BASE_QSPI0       0xf0020000
 #define ATMEL_BASE_QSPI1       0xf0024000
 #define ATMEL_BASE_SPI0                0xf8000000
@@ -117,6 +113,7 @@
 #define ATMEL_BASE_UART1       0xf8020000
 #define ATMEL_BASE_UART2       0xf8024000
 #define ATMEL_BASE_TWI0                0xf8028000
+#define ATMEL_BASE_SFR         0xf8030000
 #define ATMEL_BASE_SYSC                0xf8048000
 #define ATMEL_BASE_SPI1                0xfc000000
 #define ATMEL_BASE_UART3       0xfc008000
@@ -125,6 +122,7 @@
 #define ATMEL_BASE_UDPHS       0xfc02c000
 
 #define ATMEL_BASE_PIOA                0xfc038000
+#define ATMEL_BASE_MATRIX1     0xfc03c000
 
 #define ATMEL_CHIPID_CIDR      0xfc069000
 #define ATMEL_CHIPID_EXID      0xfc069004
@@ -132,7 +130,11 @@
 /*
  * Address Memory Space
  */
+#define ATMEL_BASE_CS0                 0x10000000
 #define ATMEL_BASE_DDRCS               0x20000000
+#define ATMEL_BASE_CS1                 0x60000000
+#define ATMEL_BASE_CS2                 0x70000000
+#define ATMEL_BASE_CS3                 0x80000000
 #define ATMEL_BASE_QSPI0_AES_MEM       0x90000000
 #define ATMEL_BASE_QSPI1_AES_MEM       0x98000000
 #define ATMEL_BASE_SDMMC0              0xa0000000
@@ -162,6 +164,7 @@
  */
 #define ATMEL_BASE_PMECC       (ATMEL_BASE_HSMC + 0x70)
 #define ATMEL_BASE_PMERRLOC    (ATMEL_BASE_HSMC + 0x500)
+#define ATMEL_BASE_SMC         (ATMEL_BASE_HSMC + 0x700)
 
 #define ATMEL_BASE_PIOB                (ATMEL_BASE_PIOA + 0x40)
 #define ATMEL_BASE_PIOC                (ATMEL_BASE_PIOB + 0x40)
@@ -171,6 +174,35 @@
 #define CPU_HAS_PCR
 #define CPU_HAS_H32MXDIV
 
+/* AICREDIR Unlock Key */
+#define ATMEL_SFR_AICREDIR_KEY         0xB6D81C4D
+
+/* MATRIX0(H64MX) slave id definitions */
+#define H64MX_SLAVE_AXIMX_BRIDGE       0       /* Bridge from H64MX to AXIMX */
+#define H64MX_SLAVE_PERIPH_BRIDGE      1       /* H64MX Peripheral Bridge */
+#define H64MX_SLAVE_DDRC_PORT0         2       /* DDR2 Port0-AESOTF */
+#define H64MX_SLAVE_DDRC_PORT1         3       /* DDR2 Port1 */
+#define H64MX_SLAVE_DDRC_PORT2         4       /* DDR2 Port2 */
+#define H64MX_SLAVE_DDRC_PORT3         5       /* DDR2 Port3 */
+#define H64MX_SLAVE_DDRC_PORT4         6       /* DDR2 Port4 */
+#define H64MX_SLAVE_DDRC_PORT5         7       /* DDR2 Port5 */
+#define H64MX_SLAVE_DDRC_PORT6         8       /* DDR2 Port6 */
+#define H64MX_SLAVE_DDRC_PORT7         9       /* DDR2 Port7 */
+#define H64MX_SLAVE_SRAM               10      /* Internal SRAM 128K */
+#define H64MX_SLAVE_CACHE_L2           11      /* Internal SRAM 128K(L2) */
+#define H64MX_SLAVE_QSPI0              12      /* QSPI0 */
+#define H64MX_SLAVE_QSPI1              13      /* QSPI1 */
+#define H64MX_SLAVE_AESB               14      /* AESB */
+
+/* MATRIX1(H32MX) slave id definitions */
+#define H32MX_SLAVE_H64MX_BRIDGE       0       /* Bridge from H32MX to H64MX */
+#define H32MX_SLAVE_PERIPH_BRIDGE0     1       /* H32MX Peripheral Bridge 0 */
+#define H32MX_SLAVE_PERIPH_BRIDGE1     2       /* H32MX Peripheral Bridge 1 */
+#define H32MX_SLAVE_EBI                        3       /* External Bus Interface */
+#define H32MX_SLAVE_NFC_CMD            3       /* NFC command Register */
+#define H32MX_SLAVE_NFC_SRAM           4       /* NFC SRAM */
+#define H32MX_SLAVE_USB                        5       /* USB Device & Host */
+
 /* SAMA5D2 series chip id definitions */
 #define ARCH_ID_SAMA5D2                0x8a5c08c0
 #define ARCH_EXID_SAMA5D21CU   0x0000005a
@@ -185,7 +217,11 @@
 #define ARCH_EXID_SAMA5D28CU   0x00000010
 #define ARCH_EXID_SAMA5D28CN   0x00000020
 
-#define cpu_is_sama5d2()       (get_chip_id() == ARCH_ID_SAMA5D2)
+#define ARCH_ID_SAMA5D2_SIP            0x8a5c08c2
+#define ARCH_EXID_SAMA5D225C_D1M       0x00000053
+#define ARCH_EXID_SAMA5D27C_D5M                0x00000032
+#define ARCH_EXID_SAMA5D27C_D1G                0x00000033
+#define ARCH_EXID_SAMA5D28C_D1G                0x00000013
 
 /* PIT Timer(PIT_PIIR) */
 #define CONFIG_SYS_TIMER_COUNTER       0xf804803c
@@ -196,6 +232,7 @@
 #ifndef __ASSEMBLY__
 unsigned int get_chip_id(void);
 unsigned int get_extension_chip_id(void);
+int cpu_is_sama5d2(void);
 unsigned int has_lcdc(void);
 char *get_cpu_name(void);
 #endif