+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Chip-specific header file for the AT91SAM9x5 family
*
*
* Definitions for the SoC:
* AT91SAM9x5 & AT91SAM9N12
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __AT91SAM9X5_H__
#define __AT91SAM9X5_H__
-#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
-
/*
* Peripheral identifiers/interrupts.
*/
#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
#endif
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000
+#define ATMEL_BASE_CS1 0x20000000
+#define ATMEL_BASE_CS2 0x30000000
+#define ATMEL_BASE_CS3 0x40000000
+#define ATMEL_BASE_CS4 0x50000000
+#define ATMEL_BASE_CS5 0x60000000
+
/* 9x5 series chip id definitions */
#define ARCH_ID_AT91SAM9X5 0x819a05a0
#define ARCH_ID_VERSION_MASK 0x1f
* Other misc defines
*/
#define ATMEL_PIO_PORTS 4
-#define CPU_HAS_PIO3
-#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
#define ATMEL_ID_UHP ATMEL_ID_UHPHS