Merge git://git.denx.de/u-boot-fsl-qoriq

[oweals/u-boot.git] / arch / arm / lib / relocate.S

diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index cd2bab6cde7fb4e9c19cedc611122b91267d2aab..a6fb07c401d47426ba914722da345dfcff2766c7 100644 (file)
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -3,26 +3,67 @@
  *
  *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
+#include <asm-offsets.h>
+#include <config.h>
+#include <elf.h>
 #include <linux/linkage.h>
+#ifdef CONFIG_CPU_V7M
+#include <asm/armv7m.h>
+#endif
+
+/*
+ * Default/weak exception vectors relocation routine
+ *
+ * This routine covers the standard ARM cases: normal (0x00000000),
+ * high (0xffff0000) and VBAR. SoCs which do not comply with any of
+ * the standard cases must provide their own, strong, version.
+ */
+
+       .section        .text.relocate_vectors,"ax",%progbits
+       .weak           relocate_vectors
+
+ENTRY(relocate_vectors)
+
+#ifdef CONFIG_CPU_V7M
+       /*
+        * On ARMv7-M we only have to write the new vector address
+        * to VTOR register.
+        */
+       ldr     r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+       ldr     r1, =V7M_SCB_BASE
+       str     r0, [r1, V7M_SCB_VTOR]
+#else
+#ifdef CONFIG_HAS_VBAR
+       /*
+        * If the ARM processor has the security extensions,
+        * use VBAR to relocate the exception vectors.
+        */
+       ldr     r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+       mcr     p15, 0, r0, c12, c0, 0  /* Set VBAR */
+#else
+       /*
+        * Copy the relocated exception vectors to the
+        * correct address
+        * CP15 c1 V bit gives us the location of the vectors:
+        * 0x00000000 or 0xFFFF0000.
+        */
+       ldr     r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+       mrc     p15, 0, r2, c1, c0, 0   /* V bit (bit[13]) in CP15 c1 */
+       ands    r2, r2, #(1 << 13)
+       ldreq   r1, =0x00000000         /* If V=0 */
+       ldrne   r1, =0xFFFF0000         /* If V=1 */
+       ldmia   r0!, {r2-r8,r10}
+       stmia   r1!, {r2-r8,r10}
+       ldmia   r0!, {r2-r8,r10}
+       stmia   r1!, {r2-r8,r10}
+#endif
+#endif
+       bx      lr
+
+ENDPROC(relocate_vectors)
 
 /*
  * void relocate_code(addr_moni)
@@ -38,7 +79,7 @@
 
 ENTRY(relocate_code)
        ldr     r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */
-       subs    r9, r0, r1              /* r9 <- relocation offset */
+       subs    r4, r0, r1              /* r4 <- relocation offset */
        beq     relocate_done           /* skip relocation */
        ldr     r2, =__image_copy_end   /* r2 <- SRC &__image_copy_end */
 
@@ -56,13 +97,13 @@ copy_loop:
 fixloop:
        ldmia   r2!, {r0-r1}            /* (r0,r1) <- (SRC location,fixup) */
        and     r1, r1, #0xff
-       cmp     r1, #23                 /* relative fixup? */
+       cmp     r1, #R_ARM_RELATIVE
        bne     fixnext
 
        /* relative fix: increase location by offset */
-       add     r0, r0, r9
+       add     r0, r0, r4
        ldr     r1, [r0]
-       add     r1, r1, r9
+       add     r1, r1, r4
        str     r1, [r0]
 fixnext:
        cmp     r2, r3
@@ -82,9 +123,9 @@ relocate_done:
        /* ARMv4- don't know bx lr but the assembler fails to see that */
 
 #ifdef __ARM_ARCH_4__
-        mov        pc, lr
+       mov     pc, lr
 #else
-        bx        lr
+       bx      lr
 #endif
 
 ENDPROC(relocate_code)