Merge branch 'master' of git://git.denx.de/u-boot-arm

[oweals/u-boot.git] / arch / arm / lib / cache-cp15.c

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 51831a96b54c5562e36f9e14c740d38e452cd345..939de10e039153d0fd1ef29cb962366d5357a355 100644 (file)
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -92,13 +92,18 @@ static inline void mmu_setup(void)
        set_cr(reg | CR_M);
 }
 
+static int mmu_enabled(void)
+{
+       return get_cr() & CR_M;
+}
+
 /* cache_bit must be either CR_I or CR_C */
 static void cache_enable(uint32_t cache_bit)
 {
        uint32_t reg;
 
        /* The data cache is not active unless the mmu is enabled too */
-       if (cache_bit == CR_C)
+       if ((cache_bit == CR_C) && !mmu_enabled())
                mmu_setup();
        reg = get_cr(); /* get control reg. */
        cp_delay();
@@ -110,17 +115,17 @@ static void cache_disable(uint32_t cache_bit)
 {
        uint32_t reg;
 
+       reg = get_cr();
+       cp_delay();
+
        if (cache_bit == CR_C) {
                /* if cache isn;t enabled no need to disable */
-               reg = get_cr();
                if ((reg & CR_C) != CR_C)
                        return;
                /* if disabling data cache, disable mmu too */
                cache_bit |= CR_M;
-               flush_cache(0, ~0);
+               flush_dcache_all();
        }
-       reg = get_cr();
-       cp_delay();
        set_cr(reg & ~cache_bit);
 }
 #endif