ARM: DRA7: DDR: Enable SR in Power Management Control

[oweals/u-boot.git] / arch / arm / include / asm / omap_common.h

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 50f178bd58b7dc01bcf44b3111ca21fe030d544b..aef31266ce9e9c386d7d84302beb3b022e7466b7 100644 (file)
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -145,6 +145,7 @@ struct prcm_regs {
        u32 cm_ssc_modfreqdiv_dpll_unipro;
        u32 cm_coreaon_usb_phy1_core_clkctrl;
        u32 cm_coreaon_usb_phy2_core_clkctrl;
+       u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
 
        /* cm2.core */
        u32 cm_coreaon_bandgap_clkctrl;
@@ -231,6 +232,7 @@ struct prcm_regs {
        u32 cm_l3init_ocp2scp1_clkctrl;
        u32 cm_l3init_ocp2scp3_clkctrl;
        u32 cm_l3init_usb_otg_ss1_clkctrl;
+       u32 cm_l3init_usb_otg_ss2_clkctrl;
 
        u32 prm_irqstatus_mpu_2;
 
@@ -313,6 +315,7 @@ struct prcm_regs {
        u32 prm_rstctrl;
        u32 prm_rstst;
        u32 prm_rsttime;
+       u32 prm_io_pmctrl;
        u32 prm_vc_val_bypass;
        u32 prm_vc_cfg_i2c_mode;
        u32 prm_vc_cfg_i2c_clk;
@@ -344,6 +347,14 @@ struct prcm_regs {
        /* GMAC Clk Ctrl */
        u32 cm_gmac_gmac_clkctrl;
        u32 cm_gmac_clkstctrl;
+
+       /* IPU */
+       u32 cm_ipu_clkstctrl;
+       u32 cm_ipu_i2c5_clkctrl;
+
+       /*l3main1 edma*/
+       u32 cm_l3main1_tptc1_clkctrl;
+       u32 cm_l3main1_tptc2_clkctrl;
 };
 
 struct omap_sys_ctrl_regs {
@@ -455,6 +466,9 @@ struct omap_sys_ctrl_regs {
        u32 control_efuse_12;
        u32 control_efuse_13;
        u32 control_padconf_wkup_base;
+       u32 iodelay_config_base;
+       u32 ctrl_core_sma_sw_0;
+       u32 ctrl_core_sma_sw_1;
 };
 
 struct dpll_params {
@@ -568,12 +582,20 @@ void do_enable_clocks(u32 const *clk_domains,
                      u32 const *clk_modules_explicit_en,
                      u8 wait_for_enable);
 
+void do_disable_clocks(u32 const *clk_domains,
+                      u32 const *clk_modules_disable,
+                      u8 wait_for_disable);
+
 void setup_post_dividers(u32 const base,
                        const struct dpll_params *params);
 u32 omap_ddr_clk(void);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
 void enable_basic_uboot_clocks(void);
+
+void enable_usb_clocks(int index);
+void disable_usb_clocks(int index);
+
 void scale_vcores(struct vcores_data const *);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
@@ -581,11 +603,23 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
               u32 txdone, u32 txdone_mask, u32 opp);
 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
 
-void usb_fake_mac_from_die_id(u32 *id);
-void usb_set_serial_num_from_die_id(u32 *id);
+void omap_die_id_serial(void);
+void omap_die_id_get_board_serial(struct tag_serialnr *serialnr);
+void omap_die_id_usbethaddr(void);
+void omap_die_id_display(void);
+
+void recalibrate_iodelay(void);
 
 void omap_smc1(u32 service, u32 val);
 
+void enable_edma3_clocks(void);
+void disable_edma3_clocks(void);
+
+void omap_die_id(unsigned int *die_id);
+
+/* Initialize general purpose I2C(0) on the SoC */
+void gpi2c_init(void);
+
 /* ABB */
 #define OMAP_ABB_NOMINAL_OPP           0
 #define OMAP_ABB_FAST_OPP              1
@@ -664,6 +698,7 @@ static inline u8 is_dra72x(void)
 /* DRA7XX */
 #define DRA752_ES1_0   0x07520100
 #define DRA752_ES1_1   0x07520110
+#define DRA752_ES2_0   0x07520200
 #define DRA722_ES1_0   0x07220100
 
 /*
@@ -678,6 +713,21 @@ static inline u8 is_dra72x(void)
 #define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
 #define OMAP_SRAM_SCRATCH_SYS_CTRL     (SRAM_SCRATCH_SPACE_ADDR + 0x20)
 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS  (SRAM_SCRATCH_SPACE_ADDR + 0x24)
-#define OMAP5_SRAM_SCRATCH_SPACE_END   (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#define OMAP_SRAM_SCRATCH_SPACE_END    (OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
+
+/* Boot parameters */
+#define DEVICE_DATA_OFFSET     0x18
+#define BOOT_MODE_OFFSET       0x8
+
+#define CH_FLAGS_CHSETTINGS    (1 << 0)
+#define CH_FLAGS_CHRAM         (1 << 1)
+#define CH_FLAGS_CHFLASH       (1 << 2)
+#define CH_FLAGS_CHMMCSD       (1 << 3)
+
+#ifndef __ASSEMBLY__
+u32 omap_sys_boot_device(void);
+#endif
 
 #endif /* _OMAP_COMMON_H_ */