Merge git://git.denx.de/u-boot-arm

[oweals/u-boot.git] / arch / arm / include / asm / imx-common / regs-apbh.h

diff --git a/arch/arm/include/asm/imx-common/regs-apbh.h b/arch/arm/include/asm/imx-common/regs-apbh.h
index a5de9276ebd3496534dc9f94181e2ce96351bcb7..ca7743600420048b5f404130dd35fcafe52f1fbe 100644 (file)
--- a/arch/arm/include/asm/imx-common/regs-apbh.h
+++ b/arch/arm/include/asm/imx-common/regs-apbh.h
@@ -7,20 +7,7 @@
  * Based on code from LTIB:
  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __REGS_APBH_H__
@@ -109,7 +96,7 @@ struct mxs_apbh_regs {
        mxs_reg_32(hw_apbh_version)
 };
 
-#elif defined(CONFIG_MX28)
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
 struct mxs_apbh_regs {
        mxs_reg_32(hw_apbh_ctrl0)
        mxs_reg_32(hw_apbh_ctrl1)
@@ -288,6 +275,17 @@ struct mxs_apbh_regs {
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND7                0x0800
 #define        APBH_CTRL0_CLKGATE_CHANNEL_HSADC                0x1000
 #define        APBH_CTRL0_CLKGATE_CHANNEL_LCDIF                0x2000
+#elif defined(CONFIG_MX6)
+#define        APBH_CTRL0_CLKGATE_CHANNEL_OFFSET               0
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND0                0x0001
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND1                0x0002
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND2                0x0004
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND3                0x0008
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND4                0x0010
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND5                0x0020
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND6                0x0040
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND7                0x0080
+#define        APBH_CTRL0_CLKGATE_CHANNEL_SSP                  0x0100
 #endif
 
 #define        APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN                 (1 << 31)
@@ -393,6 +391,10 @@ struct mxs_apbh_regs {
 #define        APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF          0x2000
 #endif
 
+#if defined(CONFIG_MX6)
+#define        APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET          16
+#endif
+
 #if defined(CONFIG_MX23)
 #define        APBH_DEVSEL_CH7_MASK                            (0xf << 28)
 #define        APBH_DEVSEL_CH7_OFFSET                          28