aspeed: Add P-Bus clock in ast2500 clock driver

[oweals/u-boot.git] / arch / arm / include / asm / imx-common / iomux-v3.h

diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index e0a49be4ff79de66abdb22e420a94b354a83e89f..ba0ed43811dad36fac286af318667d19d2337a9f 100644 (file)
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -39,10 +39,9 @@
  * MUX_CTRL_OFS:           0..11 (12)
  * PAD_CTRL_OFS:          12..23 (12)
  * SEL_INPUT_OFS:         24..35 (12)
- * MUX_MODE + SION:       36..40  (5)
- * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
- * SEL_INP:               59..62  (4)
- * reserved:                63    (1)
+ * MUX_MODE + SION + LPSR: 36..41  (6)
+ * PAD_CTRL + NO_PAD_CTRL: 42..59 (18)
+ * SEL_INP:               60..63  (4)
 */
 
 typedef u64 iomux_v3_cfg_t;
@@ -57,10 +56,10 @@ typedef u64 iomux_v3_cfg_t;
        MUX_SEL_INPUT_OFS_SHIFT)
 
 #define MUX_MODE_SHIFT         36
-#define MUX_MODE_MASK          ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
-#define MUX_PAD_CTRL_SHIFT     41
+#define MUX_MODE_MASK          ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL_SHIFT     42
 #define MUX_PAD_CTRL_MASK      ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
-#define MUX_SEL_INPUT_SHIFT    59
+#define MUX_SEL_INPUT_SHIFT    60
 #define MUX_SEL_INPUT_MASK     ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
 
 #define MUX_MODE_SION          ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
@@ -85,6 +84,36 @@ typedef u64 iomux_v3_cfg_t;
 
 #define NO_PAD_CTRL            (1 << 17)
 
+#define IOMUX_CONFIG_LPSR       0x20
+#define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
+                               MUX_MODE_SHIFT)
+#ifdef CONFIG_MX7
+
+#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
+
+#define PAD_CTL_DSE_1P8V_140OHM   (0x0<<0)
+#define PAD_CTL_DSE_1P8V_35OHM    (0x1<<0)
+#define PAD_CTL_DSE_1P8V_70OHM    (0x2<<0)
+#define PAD_CTL_DSE_1P8V_23OHM    (0x3<<0)
+
+#define PAD_CTL_DSE_3P3V_196OHM   (0x0<<0)
+#define PAD_CTL_DSE_3P3V_49OHM    (0x1<<0)
+#define PAD_CTL_DSE_3P3V_98OHM    (0x2<<0)
+#define PAD_CTL_DSE_3P3V_32OHM    (0x3<<0)
+
+#define PAD_CTL_SRE_FAST     (0 << 2)
+#define PAD_CTL_SRE_SLOW     (0x1 << 2)
+
+#define PAD_CTL_HYS       (0x1 << 3)
+#define PAD_CTL_PUE       (0x1 << 4)
+
+#define PAD_CTL_PUS_PD100KOHM  ((0x0 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU5KOHM    ((0x1 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU47KOHM   ((0x2 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU100KOHM  ((0x3 << 5) | PAD_CTL_PUE)
+
+#else
+
 #ifdef CONFIG_MX6
 
 #define PAD_CTL_HYS            (1 << 16)
@@ -98,7 +127,11 @@ typedef u64 iomux_v3_cfg_t;
 
 #define PAD_CTL_ODE            (1 << 11)
 
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
+#define PAD_CTL_SPEED_LOW      (0 << 6)
+#else
 #define PAD_CTL_SPEED_LOW      (1 << 6)
+#endif
 #define PAD_CTL_SPEED_MED      (2 << 6)
 #define PAD_CTL_SPEED_HIGH     (3 << 6)
 
@@ -111,10 +144,12 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_DSE_40ohm      (6 << 3)
 #define PAD_CTL_DSE_34ohm      (7 << 3)
 
-#if defined CONFIG_MX6SL
+/* i.MX6SL/SLL */
 #define PAD_CTL_LVE            (1 << 1)
 #define PAD_CTL_LVE_BIT                (1 << 22)
-#endif
+
+/* i.MX6SLL */
+#define PAD_CTL_IPD_BIT                (1 << 27)
 
 #elif defined(CONFIG_VF610)
 
@@ -127,8 +162,13 @@ typedef u64 iomux_v3_cfg_t;
 
 #define PAD_CTL_SRE            (1 << 11)
 
+#define PAD_CTL_ODE            (1 << 10)
+
 #define PAD_CTL_DSE_150ohm     (1 << 6)
+#define PAD_CTL_DSE_75ohm      (2 << 6)
 #define PAD_CTL_DSE_50ohm      (3 << 6)
+#define PAD_CTL_DSE_37ohm      (4 << 6)
+#define PAD_CTL_DSE_30ohm      (5 << 6)
 #define PAD_CTL_DSE_25ohm      (6 << 6)
 #define PAD_CTL_DSE_20ohm      (7 << 6)
 
@@ -167,6 +207,8 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_SRE_SLOW       (0 << 0)
 #define PAD_CTL_SRE_FAST       (1 << 0)
 
+#endif
+
 #define IOMUX_CONFIG_SION      0x10
 
 #define GPIO_PIN_MASK          0x1f
@@ -187,12 +229,18 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 */
 void imx_iomux_set_gpr_register(int group, int start_bit,
                                         int num_bits, int value);
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+                               unsigned int direction);
+void imx_iomux_gpio_get_function(unsigned int gpio,
+                               u32 *gpio_state);
+#endif
 
 /* macros for declaring and using pinmux array */
 #if defined(CONFIG_MX6QDL)
 #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
 #define SETUP_IOMUX_PAD(def)                                   \
-if (is_cpu_type(MXC_CPU_MX6Q)) {                               \
+if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {                          \
        imx_iomux_v3_setup_pad(MX6Q_##def);                     \
 } else {                                                       \
        imx_iomux_v3_setup_pad(MX6DL_##def);                    \