mx5: lowlevel_init.S: Fix PLL settings for mx53

[oweals/u-boot.git] / arch / arm / include / asm / emif.h

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index c2ad877ab2458656229ccc6ab8475e13fdedd271..ed251ec8ec19f119180e56a7be186bcc6110fbab 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -19,7 +19,7 @@
 #define EMIF1_BASE                             0x4c000000
 #define EMIF2_BASE                             0x4d000000
 
-/* Registers shifts and masks */
+/* Registers shifts, masks and values */
 
 /* EMIF_MOD_ID_REV */
 #define EMIF_REG_SCHEME_SHIFT                  30
@@ -46,6 +46,12 @@
 /* SDRAM_CONFIG */
 #define EMIF_REG_SDRAM_TYPE_SHIFT                      29
 #define EMIF_REG_SDRAM_TYPE_MASK                       (0x7 << 29)
+#define EMIF_REG_SDRAM_TYPE_DDR1                       0
+#define EMIF_REG_SDRAM_TYPE_LPDDR1                     1
+#define EMIF_REG_SDRAM_TYPE_DDR2                       2
+#define EMIF_REG_SDRAM_TYPE_DDR3                       3
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4                  4
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2                  5
 #define EMIF_REG_IBANK_POS_SHIFT                       27
 #define EMIF_REG_IBANK_POS_MASK                        (0x3 << 27)
 #define EMIF_REG_DDR_TERM_SHIFT                        24
@@ -1141,6 +1147,8 @@ void emif_get_device_timings(u32 emif_nr,
                const struct lpddr2_device_timings **cs1_device_timings);
 #endif
 
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
+
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 extern u32 *const T_num;
 extern u32 *const T_den;