mx5: lowlevel_init.S: Fix PLL settings for mx53

[oweals/u-boot.git] / arch / arm / include / asm / emif.h

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index aab15d8ef6c758a8f73c6d7805049d30ec8b5b22..ed251ec8ec19f119180e56a7be186bcc6110fbab 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -19,7 +19,7 @@
 #define EMIF1_BASE                             0x4c000000
 #define EMIF2_BASE                             0x4d000000
 
-/* Registers shifts and masks */
+/* Registers shifts, masks and values */
 
 /* EMIF_MOD_ID_REV */
 #define EMIF_REG_SCHEME_SHIFT                  30
@@ -46,6 +46,12 @@
 /* SDRAM_CONFIG */
 #define EMIF_REG_SDRAM_TYPE_SHIFT                      29
 #define EMIF_REG_SDRAM_TYPE_MASK                       (0x7 << 29)
+#define EMIF_REG_SDRAM_TYPE_DDR1                       0
+#define EMIF_REG_SDRAM_TYPE_LPDDR1                     1
+#define EMIF_REG_SDRAM_TYPE_DDR2                       2
+#define EMIF_REG_SDRAM_TYPE_DDR3                       3
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4                  4
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2                  5
 #define EMIF_REG_IBANK_POS_SHIFT                       27
 #define EMIF_REG_IBANK_POS_MASK                        (0x3 << 27)
 #define EMIF_REG_DDR_TERM_SHIFT                        24
@@ -226,8 +232,8 @@
 #define EMIF_REG_CS_TIM_MASK                   (0xf << 0)
 
 /* PWR_MGMT_CTRL_SHDW */
-#define EMIF_REG_PD_TIM_SHDW_SHIFT                     8
-#define EMIF_REG_PD_TIM_SHDW_MASK                      (0xf << 8)
+#define EMIF_REG_PD_TIM_SHDW_SHIFT                     12
+#define EMIF_REG_PD_TIM_SHDW_MASK                      (0xf << 12)
 #define EMIF_REG_SR_TIM_SHDW_SHIFT                     4
 #define EMIF_REG_SR_TIM_SHDW_MASK                      (0xf << 4)
 #define EMIF_REG_CS_TIM_SHDW_SHIFT                     0
@@ -471,6 +477,49 @@
 #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT          0
 #define EMIF_REG_DDR_PHY_CTRL_2_MASK           (0xffffffff << 0)
 
+/*EMIF_READ_WRITE_LEVELING_CONTROL*/
+#define EMIF_REG_RDWRLVLFULL_START_SHIFT       31
+#define EMIF_REG_RDWRLVLFULL_START_MASK                (1 << 31)
+#define EMIF_REG_RDWRLVLINC_PRE_SHIFT          24
+#define EMIF_REG_RDWRLVLINC_PRE_MASK           (0x7F << 24)
+#define EMIF_REG_RDLVLINC_INT_SHIFT            16
+#define EMIF_REG_RDLVLINC_INT_MASK             (0xFF << 16)
+#define EMIF_REG_RDLVLGATEINC_INT_SHIFT                8
+#define EMIF_REG_RDLVLGATEINC_INT_MASK         (0xFF << 8)
+#define EMIF_REG_WRLVLINC_INT_SHIFT            0
+#define EMIF_REG_WRLVLINC_INT_MASK             (0xFF << 0)
+
+/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/
+#define EMIF_REG_RDWRLVL_EN_SHIFT              31
+#define EMIF_REG_RDWRLVL_EN_MASK               (1 << 31)
+#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT      24
+#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK       (0x7F << 24)
+#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT                16
+#define EMIF_REG_RDLVLINC_RMP_INT_MASK         (0xFF << 16)
+#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT    8
+#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK     (0xFF << 8)
+#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT                0
+#define EMIF_REG_WRLVLINC_RMP_INT_MASK         (0xFF << 0)
+
+/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/
+#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT      0
+#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK       (0x1FFF << 0)
+
+/*Leveling Fields */
+#define DDR3_WR_LVL_INT                0x73
+#define DDR3_RD_LVL_INT                0x33
+#define DDR3_RD_LVL_GATE_INT   0x59
+#define RD_RW_LVL_INC_PRE      0x0
+#define DDR3_FULL_LVL          (1 << EMIF_REG_RDWRLVL_EN_SHIFT)
+
+#define DDR3_INC_LVL   ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT)   \
+               | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \
+               | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT)      \
+               | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT))
+
+#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES     0x0000C1A7
+#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES      0x000001A7
+
 /* DMM */
 #define DMM_BASE                       0x4E000040
 
@@ -650,6 +699,7 @@ struct dmm_lisa_map_regs {
 };
 
 extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
+extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
 
 #define CS0    0
 #define CS1    1
@@ -1073,6 +1123,10 @@ struct emif_regs {
        u32 emif_ddr_ext_phy_ctrl_3;
        u32 emif_ddr_ext_phy_ctrl_4;
        u32 emif_ddr_ext_phy_ctrl_5;
+       u32 emif_rd_wr_lvl_rmp_win;
+       u32 emif_rd_wr_lvl_rmp_ctl;
+       u32 emif_rd_wr_lvl_ctl;
+       u32 emif_rd_wr_exec_thresh;
 };
 
 /* assert macros */
@@ -1093,11 +1147,13 @@ void emif_get_device_timings(u32 emif_nr,
                const struct lpddr2_device_timings **cs1_device_timings);
 #endif
 
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
+
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 extern u32 *const T_num;
 extern u32 *const T_den;
 extern u32 *const emif_sizes;
 #endif
 
-
+void config_data_eye_leveling_samples(u32 emif_base);
 #endif