Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblaze

[oweals/u-boot.git] / arch / arm / include / asm / emif.h

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 7986e6e7949094d23995977f87f78c29435cf466..9a46340deb318a5457cdf3c32946a115fad61ed8 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -478,6 +478,12 @@
 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK  (0xFF << 4)
 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK    (0xFFFFF << 12)
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT           25
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK            (1 << 25)
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT       26
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK                (1 << 26)
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT           27
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK            (1 << 27)
 
 /* DDR_PHY_CTRL_2 */
 #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT          0
@@ -539,6 +545,9 @@
 
 /* Memory Adapter */
 #define MA_BASE                                0x482AF040
+#define MA_PRIORITY                    0x482A2000
+#define MA_HIMEM_INTERLEAVE_UN_SHIFT   8
+#define MA_HIMEM_INTERLEAVE_UN_MASK    (1 << 8)
 
 /* DMM_LISA_MAP */
 #define EMIF_SYS_ADDR_SHIFT            24
@@ -905,8 +914,8 @@ struct dmm_lisa_map_regs {
 
 /* Maximum delay before Low Power Modes */
 #define REG_CS_TIM             0x0
-#define REG_SR_TIM             0x0
-#define REG_PD_TIM             0x0
+#define REG_SR_TIM             0xF
+#define REG_PD_TIM             0xF
 
 
 /* EMIF_PWR_MGMT_CTRL register */
@@ -914,7 +923,7 @@ struct dmm_lisa_map_regs {
        ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
        ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
        ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
-       ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
+       ((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)\
                        & EMIF_REG_LP_MODE_MASK) |\
        ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
                        & EMIF_REG_DPD_EN_MASK))\
@@ -1162,6 +1171,7 @@ struct emif_regs {
        u32 sdram_tim1;
        u32 sdram_tim2;
        u32 sdram_tim3;
+       u32 ocp_config;
        u32 read_idle_ctrl;
        u32 zq_config;
        u32 temp_alert_config;