colibri_vf: Enable board specific USB initialisation for USB pen gpio

[oweals/u-boot.git] / arch / arm / include / asm / emif.h

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index d9d521a51505728eff9e04674516aba66ce3b222..7a545ea01a7c3f661867696f9c88c80fd3386dae 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -14,11 +14,15 @@
 #define _EMIF_H_
 #include <asm/types.h>
 #include <common.h>
+#include <asm/io.h>
 
 /* Base address */
 #define EMIF1_BASE                             0x4c000000
 #define EMIF2_BASE                             0x4d000000
 
+#define EMIF_4D                                        0x4
+#define EMIF_4D5                               0x5
+
 /* Registers shifts, masks and values */
 
 /* EMIF_MOD_ID_REV */
@@ -638,11 +642,16 @@ struct emif_reg_struct {
        u32 emif_ddr_phy_ctrl_1;
        u32 emif_ddr_phy_ctrl_1_shdw;
        u32 emif_ddr_phy_ctrl_2;
-       u32 padding7[12];
+       u32 padding7[4];
+       u32 emif_prio_class_serv_map;
+       u32 emif_connect_id_serv_1_map;
+       u32 emif_connect_id_serv_2_map;
+       u32 padding8[5];
        u32 emif_rd_wr_exec_thresh;
-       u32 padding8[7];
-       u32 emif_ddr_phy_status[21];
-       u32 padding9[27];
+       u32 emif_cos_config;
+       u32 padding9[6];
+       u32 emif_ddr_phy_status[28];
+       u32 padding10[20];
        u32 emif_ddr_ext_phy_ctrl_1;
        u32 emif_ddr_ext_phy_ctrl_1_shdw;
        u32 emif_ddr_ext_phy_ctrl_2;
@@ -691,9 +700,36 @@ struct emif_reg_struct {
        u32 emif_ddr_ext_phy_ctrl_23_shdw;
        u32 emif_ddr_ext_phy_ctrl_24;
        u32 emif_ddr_ext_phy_ctrl_24_shdw;
-       u32 padding[22];
-       u32 emif_ddr_fifo_misaligned_clear_1;
-       u32 emif_ddr_fifo_misaligned_clear_2;
+       u32 emif_ddr_ext_phy_ctrl_25;
+       u32 emif_ddr_ext_phy_ctrl_25_shdw;
+       u32 emif_ddr_ext_phy_ctrl_26;
+       u32 emif_ddr_ext_phy_ctrl_26_shdw;
+       u32 emif_ddr_ext_phy_ctrl_27;
+       u32 emif_ddr_ext_phy_ctrl_27_shdw;
+       u32 emif_ddr_ext_phy_ctrl_28;
+       u32 emif_ddr_ext_phy_ctrl_28_shdw;
+       u32 emif_ddr_ext_phy_ctrl_29;
+       u32 emif_ddr_ext_phy_ctrl_29_shdw;
+       u32 emif_ddr_ext_phy_ctrl_30;
+       u32 emif_ddr_ext_phy_ctrl_30_shdw;
+       u32 emif_ddr_ext_phy_ctrl_31;
+       u32 emif_ddr_ext_phy_ctrl_31_shdw;
+       u32 emif_ddr_ext_phy_ctrl_32;
+       u32 emif_ddr_ext_phy_ctrl_32_shdw;
+       u32 emif_ddr_ext_phy_ctrl_33;
+       u32 emif_ddr_ext_phy_ctrl_33_shdw;
+       u32 emif_ddr_ext_phy_ctrl_34;
+       u32 emif_ddr_ext_phy_ctrl_34_shdw;
+       u32 emif_ddr_ext_phy_ctrl_35;
+       u32 emif_ddr_ext_phy_ctrl_35_shdw;
+       union {
+               u32 emif_ddr_ext_phy_ctrl_36;
+               u32 emif_ddr_fifo_misaligned_clear_1;
+       };
+       union {
+               u32 emif_ddr_ext_phy_ctrl_36_shdw;
+               u32 emif_ddr_fifo_misaligned_clear_2;
+       };
 };
 
 struct dmm_lisa_map_regs {
@@ -869,7 +905,6 @@ struct dmm_lisa_map_regs {
        ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
        ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
        ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
-       ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
        ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
                        & EMIF_REG_LP_MODE_MASK) |\
        ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
@@ -880,8 +915,6 @@ struct dmm_lisa_map_regs {
                        & EMIF_REG_CS_TIM_SHDW_MASK) |\
        ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
                        & EMIF_REG_SR_TIM_SHDW_MASK) |\
-       ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
-                       & EMIF_REG_PD_TIM_SHDW_MASK) |\
        ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
                        & EMIF_REG_PD_TIM_SHDW_MASK))
 
@@ -1116,6 +1149,7 @@ struct emif_regs {
        u32 sdram_config;
        u32 sdram_config2;
        u32 ref_ctrl;
+       u32 ref_ctrl_final;
        u32 sdram_tim1;
        u32 sdram_tim2;
        u32 sdram_tim3;
@@ -1133,6 +1167,10 @@ struct emif_regs {
        u32 emif_rd_wr_lvl_rmp_ctl;
        u32 emif_rd_wr_lvl_ctl;
        u32 emif_rd_wr_exec_thresh;
+       u32 emif_prio_class_serv_map;
+       u32 emif_connect_id_serv_1_map;
+       u32 emif_connect_id_serv_2_map;
+       u32 emif_cos_config;
 };
 
 struct lpddr2_mr_regs {
@@ -1148,6 +1186,28 @@ struct read_write_regs {
        u32 write_reg;
 };
 
+static inline u32 get_emif_rev(u32 base)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+       return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
+               >> EMIF_REG_MAJOR_REVISION_SHIFT;
+}
+
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+static inline u32 emif_sdram_type(void)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+       return (readl(&emif->emif_sdram_config) &
+               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
+
 /* assert macros */
 #if defined(DEBUG)
 #define emif_assert(c) ({ if (!(c)) for (;;); })