sunxi: Move clock_get_pllX / clock_set_pllX protos to mach specific headers

[oweals/u-boot.git] / arch / arm / include / asm / emif.h

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 45668ca4dd737f7f0533f8bb363400dbf9f6e57d..342f045f41419471adea238aed0fcb309e7185d2 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -642,11 +642,16 @@ struct emif_reg_struct {
        u32 emif_ddr_phy_ctrl_1;
        u32 emif_ddr_phy_ctrl_1_shdw;
        u32 emif_ddr_phy_ctrl_2;
-       u32 padding7[12];
+       u32 padding7[4];
+       u32 emif_prio_class_serv_map;
+       u32 emif_connect_id_serv_1_map;
+       u32 emif_connect_id_serv_2_map;
+       u32 padding8[5];
        u32 emif_rd_wr_exec_thresh;
-       u32 padding8[7];
-       u32 emif_ddr_phy_status[21];
-       u32 padding9[27];
+       u32 emif_cos_config;
+       u32 padding9[6];
+       u32 emif_ddr_phy_status[28];
+       u32 padding10[20];
        u32 emif_ddr_ext_phy_ctrl_1;
        u32 emif_ddr_ext_phy_ctrl_1_shdw;
        u32 emif_ddr_ext_phy_ctrl_2;
@@ -695,9 +700,36 @@ struct emif_reg_struct {
        u32 emif_ddr_ext_phy_ctrl_23_shdw;
        u32 emif_ddr_ext_phy_ctrl_24;
        u32 emif_ddr_ext_phy_ctrl_24_shdw;
-       u32 padding[22];
-       u32 emif_ddr_fifo_misaligned_clear_1;
-       u32 emif_ddr_fifo_misaligned_clear_2;
+       u32 emif_ddr_ext_phy_ctrl_25;
+       u32 emif_ddr_ext_phy_ctrl_25_shdw;
+       u32 emif_ddr_ext_phy_ctrl_26;
+       u32 emif_ddr_ext_phy_ctrl_26_shdw;
+       u32 emif_ddr_ext_phy_ctrl_27;
+       u32 emif_ddr_ext_phy_ctrl_27_shdw;
+       u32 emif_ddr_ext_phy_ctrl_28;
+       u32 emif_ddr_ext_phy_ctrl_28_shdw;
+       u32 emif_ddr_ext_phy_ctrl_29;
+       u32 emif_ddr_ext_phy_ctrl_29_shdw;
+       u32 emif_ddr_ext_phy_ctrl_30;
+       u32 emif_ddr_ext_phy_ctrl_30_shdw;
+       u32 emif_ddr_ext_phy_ctrl_31;
+       u32 emif_ddr_ext_phy_ctrl_31_shdw;
+       u32 emif_ddr_ext_phy_ctrl_32;
+       u32 emif_ddr_ext_phy_ctrl_32_shdw;
+       u32 emif_ddr_ext_phy_ctrl_33;
+       u32 emif_ddr_ext_phy_ctrl_33_shdw;
+       u32 emif_ddr_ext_phy_ctrl_34;
+       u32 emif_ddr_ext_phy_ctrl_34_shdw;
+       u32 emif_ddr_ext_phy_ctrl_35;
+       u32 emif_ddr_ext_phy_ctrl_35_shdw;
+       union {
+               u32 emif_ddr_ext_phy_ctrl_36;
+               u32 emif_ddr_fifo_misaligned_clear_1;
+       };
+       union {
+               u32 emif_ddr_ext_phy_ctrl_36_shdw;
+               u32 emif_ddr_fifo_misaligned_clear_2;
+       };
 };
 
 struct dmm_lisa_map_regs {
@@ -873,7 +905,6 @@ struct dmm_lisa_map_regs {
        ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
        ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
        ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
-       ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
        ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
                        & EMIF_REG_LP_MODE_MASK) |\
        ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
@@ -884,8 +915,6 @@ struct dmm_lisa_map_regs {
                        & EMIF_REG_CS_TIM_SHDW_MASK) |\
        ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
                        & EMIF_REG_SR_TIM_SHDW_MASK) |\
-       ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
-                       & EMIF_REG_PD_TIM_SHDW_MASK) |\
        ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
                        & EMIF_REG_PD_TIM_SHDW_MASK))
 
@@ -1137,6 +1166,10 @@ struct emif_regs {
        u32 emif_rd_wr_lvl_rmp_ctl;
        u32 emif_rd_wr_lvl_ctl;
        u32 emif_rd_wr_exec_thresh;
+       u32 emif_prio_class_serv_map;
+       u32 emif_connect_id_serv_1_map;
+       u32 emif_connect_id_serv_2_map;
+       u32 emif_cos_config;
 };
 
 struct lpddr2_mr_regs {