Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[oweals/u-boot.git] / arch / arm / include / asm / emif.h

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index fd530bb26a089cafd14f2cdfb02df6461e72c533..1b94a99c54d46440f87e2907cb329e911153ef59 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -519,6 +519,7 @@
 
 #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES     0x0000C1A7
 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES      0x000001A7
+#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7
 
 /* DMM */
 #define DMM_BASE                       0x4E000040
@@ -580,7 +581,7 @@
        (0xFF << EMIF_SYS_ADDR_SHIFT))
 
 #define EMIF_EXT_PHY_CTRL_TIMING_REG   0x5
-#define EMIF_EXT_PHY_CTRL_CONST_REG    0x13
+#define EMIF_EXT_PHY_CTRL_CONST_REG    0x14
 
 /* Reg mapping structure */
 struct emif_reg_struct {
@@ -696,6 +697,7 @@ struct dmm_lisa_map_regs {
        u32 dmm_lisa_map_1;
        u32 dmm_lisa_map_2;
        u32 dmm_lisa_map_3;
+       u8 is_ma_present;
 };
 
 #define CS0    0
@@ -853,13 +855,10 @@ struct dmm_lisa_map_regs {
 #define DPD_ENABLE     1
 
 /* Maximum delay before Low Power Modes */
-#ifndef CONFIG_OMAP54XX
-#define REG_CS_TIM             0xF
-#else
 #define REG_CS_TIM             0x0
-#endif
-#define REG_SR_TIM             0xF
-#define REG_PD_TIM             0xF
+#define REG_SR_TIM             0x0
+#define REG_PD_TIM             0x0
+
 
 /* EMIF_PWR_MGMT_CTRL register */
 #define EMIF_PWR_MGMT_CTRL (\
@@ -1111,6 +1110,7 @@ struct emif_regs {
        u32 freq;
        u32 sdram_config_init;
        u32 sdram_config;
+       u32 sdram_config2;
        u32 ref_ctrl;
        u32 sdram_tim1;
        u32 sdram_tim2;
@@ -1163,7 +1163,6 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 extern u32 *const T_num;
 extern u32 *const T_den;
-extern u32 *const emif_sizes;
 #endif
 
 void config_data_eye_leveling_samples(u32 emif_base);