Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblaze

[oweals/u-boot.git] / arch / arm / include / asm / assembler.h

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 5e4789b1452079fee12ff63c923ecdf9bcf17115..b146918586015da8229ac85cd5662d83b927e6fd 100644 (file)
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -14,12 +14,15 @@
  *  assembler source.
  */
 
+#include <config.h>
+#include <asm/unified.h>
+
 /*
  * Endian independent macros for shifting bytes within registers.
  */
 #ifndef __ARMEB__
-#define pull           lsr
-#define push           lsl
+#define lspull         lsr
+#define lspush         lsl
 #define get_byte_0     lsl #0
 #define get_byte_1     lsr #8
 #define get_byte_2     lsr #16
@@ -29,8 +32,8 @@
 #define put_byte_2     lsl #16
 #define put_byte_3     lsl #24
 #else
-#define pull           lsl
-#define push           lsr
+#define lspull         lsl
+#define lspush         lsr
 #define get_byte_0     lsr #24
 #define get_byte_1     lsr #16
 #define get_byte_2     lsr #8
@@ -55,6 +58,27 @@
 #endif
 
 /*
- * Cache alligned
+ * We only support cores that support at least Thumb-1 and thus we use
+ * 'bx lr'
+ */
+       .irp    c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
+       .macro  ret\c, reg
+       .ifeqs  "\reg", "lr"
+       bx\c    \reg
+       .else
+       mov\c   pc, \reg
+       .endif
+       .endm
+       .endr
+
+/*
+ * Cache aligned, used for optimized memcpy/memset
+ * In the kernel this is only enabled for Feroceon CPU's...
+ * We disable it especially for Thumb builds since those instructions
+ * are not made in a Thumb ready way...
  */
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+#define CALGN(code...)
+#else
 #define CALGN(code...) code
+#endif