arm64: zynqmp: Show reset reason

[oweals/u-boot.git] / arch / arm / include / asm / arch-zynqmp / hardware.h

diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 327046bf1b29f4f406c996dc52ccd26bbb474564..f31725030b55dcaad46aa38332f22c3b252cbf5e 100644 (file)
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
  * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _ASM_ARCH_HARDWARE_H
@@ -18,9 +17,6 @@
 
 #define ARASAN_NAND_BASEADDR   0xFF100000
 
-#define ZYNQMP_USB0_XHCI_BASEADDR      0xFE200000
-#define ZYNQMP_USB1_XHCI_BASEADDR      0xFE300000
-
 #define ZYNQMP_TCM_BASE_ADDR   0xFFE00000
 #define ZYNQMP_TCM_SIZE                0x40000
 
@@ -34,6 +30,14 @@
 #define PS_MODE2       BIT(2)
 #define PS_MODE3       BIT(3)
 
+#define RESET_REASON_DEBUG_SYS BIT(6)
+#define RESET_REASON_SOFT      BIT(5)
+#define RESET_REASON_SRST      BIT(4)
+#define RESET_REASON_PSONLY    BIT(3)
+#define RESET_REASON_PMU       BIT(2)
+#define RESET_REASON_INTERNAL  BIT(1)
+#define RESET_REASON_EXTERNAL  BIT(0)
+
 struct crlapb_regs {
        u32 reserved0[36];
        u32 cpu_r5_ctrl; /* 0x90 */
@@ -41,7 +45,9 @@ struct crlapb_regs {
        u32 timestamp_ref_ctrl; /* 0x128 */
        u32 reserved2[53];
        u32 boot_mode; /* 0x200 */
-       u32 reserved3[14];
+       u32 reserved3_0[7];
+       u32 reset_reason; /* 0x220 */
+       u32 reserved3_1[6];
        u32 rst_lpd_top; /* 0x23C */
        u32 reserved4[4];
        u32 boot_pin_ctrl; /* 0x250 */