Revert "stm32: Change USART port to USART6 for stm32f746 discovery board"

[oweals/u-boot.git] / arch / arm / include / asm / arch-zynqmp / hardware.h

diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index c9dc49d783173db819352c218153e4a472a93ee4..35964d603b386c16b6ab93a3c5d0ff038faf5cb0 100644 (file)
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -8,17 +8,20 @@
 #ifndef _ASM_ARCH_HARDWARE_H
 #define _ASM_ARCH_HARDWARE_H
 
-#define ZYNQ_SERIAL_BASEADDR0  0xFF000000
-#define ZYNQ_SERIAL_BASEADDR1  0xFF001000
-
-#define ZYNQ_SPI_BASEADDR0     0xFF040000
-#define ZYNQ_SPI_BASEADDR1     0xFF050000
+#define ZYNQ_GEM_BASEADDR0     0xFF0B0000
+#define ZYNQ_GEM_BASEADDR1     0xFF0C0000
+#define ZYNQ_GEM_BASEADDR2     0xFF0D0000
+#define ZYNQ_GEM_BASEADDR3     0xFF0E0000
 
 #define ZYNQ_I2C_BASEADDR0     0xFF020000
 #define ZYNQ_I2C_BASEADDR1     0xFF030000
 
-#define ZYNQ_SDHCI_BASEADDR0   0xFF160000
-#define ZYNQ_SDHCI_BASEADDR1   0xFF170000
+#define ARASAN_NAND_BASEADDR   0xFF100000
+
+#define ZYNQMP_SATA_BASEADDR   0xFD0C0000
+
+#define ZYNQMP_USB0_XHCI_BASEADDR      0xFE200000
+#define ZYNQMP_USB1_XHCI_BASEADDR      0xFE300000
 
 #define ZYNQMP_CRL_APB_BASEADDR        0xFF5E0000
 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT       0x1000000
@@ -37,6 +40,7 @@ struct crlapb_regs {
 
 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
 
+#define ZYNQMP_IOU_SCNTR_SECURE        0xFF260000
 #define ZYNQMP_IOU_SCNTR       0xFF250000
 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN   0x1
 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
@@ -49,12 +53,33 @@ struct iou_scntr {
 
 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
 
+struct iou_scntr_secure {
+       u32 counter_control_register;
+       u32 reserved0[7];
+       u32 base_frequency_id_register;
+};
+
+#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
+
 /* Bootmode setting values */
 #define BOOT_MODES_MASK        0x0000000F
-#define SD_MODE                0x00000003
+#define QSPI_MODE_24BIT        0x00000001
+#define QSPI_MODE_32BIT        0x00000002
+#define SD_MODE                0x00000003 /* sd 0 */
+#define SD_MODE1       0x00000005 /* sd 1 */
+#define NAND_MODE      0x00000004
 #define EMMC_MODE      0x00000006
 #define JTAG_MODE      0x00000000
 
+#define ZYNQMP_IOU_SLCR_BASEADDR       0xFF180000
+
+struct iou_slcr_regs {
+       u32 mio_pin[78];
+       u32 reserved[442];
+};
+
+#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
+
 #define ZYNQMP_RPU_BASEADDR    0xFF9A0000
 
 struct rpu_regs {
@@ -89,9 +114,20 @@ struct apu_regs {
 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
 
 /* Board version value */
+#define ZYNQMP_CSU_BASEADDR            0xFFCA0000
 #define ZYNQMP_CSU_VERSION_SILICON     0x0
 #define ZYNQMP_CSU_VERSION_EP108       0x1
 #define ZYNQMP_CSU_VERSION_VELOCE      0x2
 #define ZYNQMP_CSU_VERSION_QEMU                0x3
 
+#define ZYNQMP_SILICON_VER_MASK                0xF000
+#define ZYNQMP_SILICON_VER_SHIFT       12
+
+struct csu_regs {
+       u32 reserved0[17];
+       u32 version;
+};
+
+#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
+
 #endif /* _ASM_ARCH_HARDWARE_H */