i.MX6: define struct pwm_regs and PWMCR_* defines

[oweals/u-boot.git] / arch / arm / include / asm / arch-vf610 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index c9df32a21d7f419ee60ce9d100a827e1ac30d9d9..bd6f680b63baaa00ffb01b27291f38461494441f 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -1,20 +1,7 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __ASM_ARCH_IMX_REGS_H__
@@ -98,11 +85,15 @@
 #define ESDHC0_BASE_ADDR       (AIPS1_BASE_ADDR + 0x00031000)
 #define ESDHC1_BASE_ADDR       (AIPS1_BASE_ADDR + 0x00032000)
 #define ENET_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00050000)
+#define ENET1_BASE_ADDR                (AIPS1_BASE_ADDR + 0x00051000)
+
+#define QSPI0_AMBA_BASE                0x20000000
 
 /* MUX mode and PAD ctrl are in one register */
 #define CONFIG_IOMUX_SHARE_CONF_REG
 
 #define FEC_QUIRK_ENET_MAC
+#define I2C_QUIRK_REG
 
 /* MSCM interrupt rounter */
 #define MSCM_IRSPRC_CP0_EN                             1
@@ -226,6 +217,7 @@
 #define DDRMC_CR139_PHY_WRLV_EN(v)                     ((v) & 0xff)
 #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v)       (((v) & 0x1f) << 27)
 #define DDRMC_CR154_PAD_ZQ_MODE(v)                     (((v) & 0x3) << 21)
+#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v)               (((v) & 0x3) << 18)
 #define DDRMC_CR155_AXI0_AWCACHE                       (1 << 10)
 #define DDRMC_CR155_PAD_ODT_BYTE1(v)                   ((v) & 0x7)
 #define DDRMC_CR158_TWR(v)                             ((v) & 0x3f)