/* 88 */
PERIPH_ID_CRAM2,
+ PERIPH_ID_SYNC_CLK_DOUBLER,
+ PERIPH_ID_CLK_M_DOUBLER,
+ PERIPH_ID_RESERVED91,
+ PERIPH_ID_SUS_OUT,
+ PERIPH_ID_DEV2_OUT,
+ PERIPH_ID_DEV1_OUT,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
};
+enum pll_out_id {
+ PLL_OUT1,
+ PLL_OUT2,
+ PLL_OUT3,
+ PLL_OUT4
+};
+
/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
#define PERIPH_REG(id) ((id) >> 5)