Merge commit '7b2fac7654f7420c2787f74ec3b1540fa3b343e9'

[oweals/u-boot.git] / arch / arm / include / asm / arch-tegra2 / clk_rst.h

diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h
index 6d573bf46581e059a5ea2d28a7c8995ff65685e1..36e27b5f3fa72cc087b2de9cf826dbe71651e33d 100644 (file)
--- a/arch/arm/include/asm/arch-tegra2/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -149,6 +149,9 @@ struct clk_rst_ctlr {
        uint crc_clk_src_csite;         /*_CSITE_0,             0x1D4 */
        uint crc_reserved19[9];         /*                      0x1D8-1F8 */
        uint crc_clk_src_osc;           /*_OSC_0,               0x1FC */
+       uint crc_reserved20[80];        /*                      0x200-33C */
+       uint crc_cpu_cmplx_set;         /* _CPU_CMPLX_SET_0,    0x340 */
+       uint crc_cpu_cmplx_clr;         /* _CPU_CMPLX_CLR_0,    0x344 */
 };
 
 #define PLL_BYPASS             (1 << 31)
@@ -157,9 +160,40 @@ struct clk_rst_ctlr {
 #define PLL_DIVP               (1 << 20)       /* post divider, b22:20 */
 #define PLL_DIVM               0x0C            /* input divider, b4:0 */
 
-#define SWR_UARTD_RST          (1 << 2)
-#define CLK_ENB_UARTD          (1 << 2)
+#define SWR_UARTD_RST          (1 << 1)
+#define CLK_ENB_UARTD          (1 << 1)
 #define SWR_UARTA_RST          (1 << 6)
 #define CLK_ENB_UARTA          (1 << 6)
 
+#define SWR_CPU_RST            (1 << 0)
+#define CLK_ENB_CPU            (1 << 0)
+#define SWR_CSITE_RST          (1 << 9)
+#define CLK_ENB_CSITE          (1 << 9)
+
+#define SET_CPURESET0          (1 << 0)
+#define SET_DERESET0           (1 << 4)
+#define SET_DBGRESET0          (1 << 12)
+
+#define SET_CPURESET1          (1 << 1)
+#define SET_DERESET1           (1 << 5)
+#define SET_DBGRESET1          (1 << 13)
+
+#define CLR_CPURESET0          (1 << 0)
+#define CLR_DERESET0           (1 << 4)
+#define CLR_DBGRESET0          (1 << 12)
+
+#define CLR_CPURESET1          (1 << 1)
+#define CLR_DERESET1           (1 << 5)
+#define CLR_DBGRESET1          (1 << 13)
+
+#define CPU0_CLK_STP           (1 << 8)
+#define CPU1_CLK_STP           (1 << 9)
+
+#define CPCON                  (1 << 8)
+
+#define SWR_SDMMC4_RST         (1 << 15)
+#define CLK_ENB_SDMMC4         (1 << 15)
+#define SWR_SDMMC3_RST         (1 << 5)
+#define CLK_ENB_SDMMC3         (1 << 5)
+
 #endif /* CLK_RST_H */