tegra124: video: Add full link training for eDP

[oweals/u-boot.git] / arch / arm / include / asm / arch-tegra / tegra_i2c.h

diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h
index 26507447185f8285d61ddc56508be6f7d6a66f9e..eeeb247d5d5836159f99cd3d70254ec41e70c68f 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h
@@ -105,6 +105,7 @@ struct i2c_ctlr {
        u32 sl_delay_count;             /* 3C: I2C_I2C_SL_DELAY_COUNT */
        u32 reserved_2[4];              /* 40: */
        struct i2c_control control;     /* 50 ~ 68 */
+       u32 clk_div;                    /* 6C: I2C_I2C_CLOCK_DIVISOR */
 };
 
 /* bit fields definitions for IO Packet Header 1 format */
@@ -123,6 +124,8 @@ struct i2c_ctlr {
 /* bit fields definitions for IO Packet Header 3 format */
 #define PKT_HDR3_READ_MODE_SHIFT       19
 #define PKT_HDR3_READ_MODE_MASK                (1 << PKT_HDR3_READ_MODE_SHIFT)
+#define PKT_HDR3_REPEAT_START_SHIFT    16
+#define PKT_HDR3_REPEAT_START_MASK     (1 << PKT_HDR3_REPEAT_START_SHIFT)
 #define PKT_HDR3_SLAVE_ADDR_SHIFT      0
 #define PKT_HDR3_SLAVE_ADDR_MASK       (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
 
@@ -154,11 +157,16 @@ struct i2c_ctlr {
 #define I2C_INT_ARBITRATION_LOST_SHIFT 2
 #define I2C_INT_ARBITRATION_LOST_MASK  (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
 
+/* I2C_CLK_DIVISOR_REGISTER */
+#define CLK_DIV_STD_FAST_MODE          0x19
+#define CLK_DIV_HS_MODE                        1
+#define CLK_MULT_STD_FAST_MODE         8
+
 /**
  * Returns the bus number of the DVC controller
  *
  * @return number of bus, or -1 if there is no DVC active
  */
-int tegra_i2c_get_dvc_bus_num(void);
+int tegra_i2c_get_dvc_bus(struct udevice **busp);
 
 #endif /* _TEGRA_I2C_H_ */