ARM: tegra: pass just partition ID to power_partition()

[oweals/u-boot.git] / arch / arm / include / asm / arch-tegra / pmc.h

diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index b1d47cd2e3ef24949ce9f475bd2618a992056e99..9f05a14c175749015c447681834307beaa0cd7cd 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -1,24 +1,8 @@
 /*
- *  (C) Copyright 2010,2011
+ *  (C) Copyright 2010,2011,2014
  *  NVIDIA Corporation <www.nvidia.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _PMC_H_
@@ -37,7 +21,11 @@ struct pmc_ctlr {
        uint pmc_dpd_sample;            /* _DPD_PADS_SAMPLE_0, offset 20 */
        uint pmc_dpd_enable;            /* _DPD_PADS_ENABLE_0, offset 24 */
        uint pmc_pwrgate_timer_off;     /* _PWRGATE_TIMER_OFF_0, offset 28 */
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
        uint pmc_pwrgate_timer_on;      /* _PWRGATE_TIMER_ON_0, offset 2C */
+#else
+       uint pmc_clamp_status;          /* _CLAMP_STATUS_0, offset 2C */
+#endif
        uint pmc_pwrgate_toggle;        /* _PWRGATE_TOGGLE_0, offset 30 */
        uint pmc_remove_clamping;       /* _REMOVE_CLAMPING_CMD_0, offset 34 */
        uint pmc_pwrgate_status;        /* _PWRGATE_STATUS_0, offset 38 */
@@ -128,5 +116,10 @@ struct pmc_ctlr {
 #define START_CP       (1 << 8)
 
 #define CPUPWRREQ_OE   (1 << 16)
+#define CPUPWRREQ_POL  (1 << 15)
+
+#define CRAIL          0
+#define CE0            14
+#define C0NC           15
 
 #endif /* PMC_H */