#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
+#define PRCM_SEC_SWITCH_APB0_CLK_NONSEC (0x1 << 0)
+#define PRCM_SEC_SWITCH_PLL_CFG_NONSEC (0x1 << 1)
+#define PRCM_SEC_SWITCH_PWR_GATE_NONSEC (0x1 << 2)
+
#ifndef __ASSEMBLY__
-struct sunxi_prcm_reg {
+#include <linux/compiler.h>
+
+struct __packed sunxi_prcm_reg {
u32 cpus_cfg; /* 0x000 */
u8 res0[0x8]; /* 0x004 */
u32 apb0_ratio; /* 0x00c */
u32 gpu_pwroff; /* 0x118 */
u8 res9[0x4]; /* 0x11c */
u32 vdd_pwr_reset; /* 0x120 */
- u8 res10[0x20]; /* 0x124 */
- u32 cpu1_pwr_clamp; /* 0x144 */
- u32 cpu2_pwr_clamp; /* 0x148 */
- u32 cpu3_pwr_clamp; /* 0x14c */
+ u8 res10[0x1c]; /* 0x124 */
+ u32 cpu_pwr_clamp[4]; /* 0x140 but first one is actually unused */
u8 res11[0x30]; /* 0x150 */
u32 dram_pwr; /* 0x180 */
u8 res12[0xc]; /* 0x184 */
u32 dram_tst; /* 0x190 */
+ u8 res13[0x3c]; /* 0x194 */
+ u32 prcm_sec_switch; /* 0x1d0 */
};
void prcm_apb0_enable(u32 flags);
+void prcm_apb0_disable(u32 flags);
+
#endif /* __ASSEMBLY__ */
#endif /* _PRCM_H */