#define SUN5I_GPB_TWI2 2
#define SUN4I_GPB_UART0 2
#define SUN5I_GPB_UART0 2
+#define SUN8I_GPB_UART2 2
+
+#define SUNXI_GPC_NAND 2
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
#define SUN8I_GPH_TWI1 2
#define SUN6I_GPH_TWI2 2
#define SUN6I_GPH_UART0 2
+#define SUN9I_GPH_UART0 2
#define SUNXI_GPI_SDC3 2
#define SUN7I_GPI_TWI3 3
#define SUNXI_GPIO_PULL_DOWN 2
/* Virtual AXP0 GPIOs */
-#define SUNXI_GPIO_AXP0_VBUS_DETECT 8
-#define SUNXI_GPIO_AXP0_VBUS_ENABLE 9
+#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
+#define SUNXI_GPIO_AXP0_VBUS_DETECT 4
+#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5
+#define SUNXI_GPIO_AXP0_GPIO_COUNT 6
void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
static inline int axp_gpio_init(void) { return 0; }
#endif
-struct udevice;
-
-int axp_gpio_direction_input(struct udevice *dev, unsigned offset);
-int axp_gpio_direction_output(struct udevice *dev, unsigned offset, int val);
-int axp_gpio_get_value(struct udevice *dev, unsigned offset);
-int axp_gpio_set_value(struct udevice *dev, unsigned offset, int val);
-
#endif /* _SUNXI_GPIO_H */