Merge branch 'master' of git://git.denx.de/u-boot-mmc

[oweals/u-boot.git] / arch / arm / include / asm / arch-sunxi / dram_sun8i_a83t.h

diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
index 2891b71b334eb144c7a0ec5715b0898533cc36d7..842ad3cc636ee83e784593826348a75e595ee811 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
@@ -186,7 +186,7 @@ struct sunxi_mctl_ctl_reg {
 #define MCTL_CR_BUSW8                  (0 << 12)
 #define MCTL_CR_BUSW16                 (1 << 12)
 #define MCTL_CR_SEQUENCE               (1 << 15)
-#define MCTL_CR_DDR3                   (3 << 16)
+#define MCTL_CR_DRAM_TYPE(x)           ((x) << 16)
 #define MCTL_CR_CHANNEL_MASK           (1 << 19)
 #define MCTL_CR_CHANNEL(x)             (((x) - 1) << 19)
 #define MCTL_CR_UNKNOWN                        (0x4 << 20)
@@ -198,4 +198,11 @@ struct sunxi_mctl_ctl_reg {
 #define MCTL_MR2                       0x18 /* CWL=8 */
 #define MCTL_MR3                       0x0
 
+#define MCTL_LPDDR3_MR0                        0x0
+#define MCTL_LPDDR3_MR1                        0xc3    /* twr=8, bl=8 */
+#define MCTL_LPDDR3_MR2                        0xa     /* RL=12, CWL=6 */
+#define MCTL_LPDDR3_MR3                        0x0
+
+#define DRAM_TYPE_DDR3         3
+#define DRAM_TYPE_LPDDR3       7
 #endif /* _SUNXI_DRAM_SUN8I_A83T_H */