sunxi: H6: Add DDR3 support to DRAM controller driver

[oweals/u-boot.git] / arch / arm / include / asm / arch-sunxi / dram_sun50i_h6.h

diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
index 54c475555663881999ec12685348438cf948dc8c..0a1da023760ddd329038e018d1ed7c2f659bd056 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
@@ -9,6 +9,8 @@
 #ifndef _SUNXI_DRAM_SUN50I_H6_H
 #define _SUNXI_DRAM_SUN50I_H6_H
 
+#include <stdbool.h>
+
 enum sunxi_dram_type {
        SUNXI_DRAM_TYPE_DDR3 = 3,
        SUNXI_DRAM_TYPE_DDR4,
@@ -16,6 +18,11 @@ enum sunxi_dram_type {
        SUNXI_DRAM_TYPE_LPDDR3,
 };
 
+static inline bool sunxi_dram_is_lpddr(int type)
+{
+       return type >= SUNXI_DRAM_TYPE_LPDDR2;
+}
+
 /*
  * The following information is mainly retrieved by disassembly and some FPGA
  * test code of sun50iw3 platform.
@@ -286,6 +293,7 @@ check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0);
 #define DCR_DDR3       (3 << 0)
 #define DCR_DDR4       (4 << 0)
 #define DCR_DDR8BANK   BIT(3)
+#define DCR_DDR2T      BIT(28)
 
 /*
  * The delay parameters allow to allegedly specify delay times of some