#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
+#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
+/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */
+#define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200)
+
#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000)
#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000)
#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000)
#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000)
#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000)
+#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000)
+#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000)
+#define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000)
+#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000)
+#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000)
+
/* AHB1 Module */
#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000)
#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000)