Merge branch 'master' of http://git.denx.de/u-boot-sparc

[oweals/u-boot.git] / arch / arm / include / asm / arch-sunxi / clock_sun6i.h

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index a197345540a7bdf92a7553ec749e2689e5dc5acc..09337a1deaf9b4670c8f0f7406c5a350f5423c13 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -201,13 +201,30 @@ struct sunxi_ccm_reg {
 #define CCM_PLL6_CTRL_N_MASK           (0x1f << CCM_PLL6_CTRL_N_SHIFT)
 #define CCM_PLL6_CTRL_K_SHIFT          4
 #define CCM_PLL6_CTRL_K_MASK           (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_LOCK             (1 << 28)
+
+#define CCM_MIPI_PLL_CTRL_M_SHIFT      0
+#define CCM_MIPI_PLL_CTRL_M_MASK       (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)
+#define CCM_MIPI_PLL_CTRL_M(n)         ((((n) - 1) & 0xf) << 0)
+#define CCM_MIPI_PLL_CTRL_K_SHIFT      4
+#define CCM_MIPI_PLL_CTRL_K_MASK       (0x3 << CCM_MIPI_PLL_CTRL_K_SHIFT)
+#define CCM_MIPI_PLL_CTRL_K(n)         ((((n) - 1) & 0x3) << 4)
+#define CCM_MIPI_PLL_CTRL_N_SHIFT      8
+#define CCM_MIPI_PLL_CTRL_N_MASK       (0xf << CCM_MIPI_PLL_CTRL_N_SHIFT)
+#define CCM_MIPI_PLL_CTRL_N(n)         ((((n) - 1) & 0xf) << 8)
+#define CCM_MIPI_PLL_CTRL_LDO_EN       (0x3 << 22)
+#define CCM_MIPI_PLL_CTRL_EN           (0x1 << 31)
 
 #define CCM_PLL11_CTRL_N(n)            ((((n) - 1) & 0x3f) << 8)
 #define CCM_PLL11_CTRL_SIGMA_DELTA_EN  (0x1 << 24)
 #define CCM_PLL11_CTRL_UPD             (0x1 << 30)
 #define CCM_PLL11_CTRL_EN              (0x1 << 31)
 
-#define AHB1_ABP1_DIV_DEFAULT          0x00002020
+#if defined CONFIG_MACH_SUN8I_H3
+#define AHB1_ABP1_DIV_DEFAULT          0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
+#else
+#define AHB1_ABP1_DIV_DEFAULT          0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */
+#endif
 
 #define AXI_GATE_OFFSET_DRAM           0
 
@@ -270,6 +287,9 @@ struct sunxi_ccm_reg {
 #define CCM_DRAMCLK_CFG_DIV_MASK       (0xf << 0)
 #define CCM_DRAMCLK_CFG_DIV0(x)                ((x - 1) << 8)
 #define CCM_DRAMCLK_CFG_DIV0_MASK      (0xf << 8)
+#define CCM_DRAMCLK_CFG_SRC_PLL5       (0x0 << 20)
+#define CCM_DRAMCLK_CFG_SRC_PLL6x2     (0x1 << 20)
+#define CCM_DRAMCLK_CFG_SRC_MASK       (0x3 << 20)
 #define CCM_DRAMCLK_CFG_UPD            (0x1 << 16)
 #define CCM_DRAMCLK_CFG_RST            (0x1 << 31)
 
@@ -364,8 +384,10 @@ void clock_set_pll1(unsigned int hz);
 void clock_set_pll3(unsigned int hz);
 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
+void clock_set_mipi_pll(unsigned int hz);
 unsigned int clock_get_pll3(void);
 unsigned int clock_get_pll6(void);
+unsigned int clock_get_mipi_pll(void);
 #endif
 
 #endif /* _SUNXI_CLOCK_SUN6I_H */