sunxi: display: Add a few extra register and constant defines

[oweals/u-boot.git] / arch / arm / include / asm / arch-sunxi / clock_sun6i.h

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index bacd70adf60f79bb629b734cca80782ca5f7063b..06c6febba597129196760b949e5fac637d43b205 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -215,11 +215,14 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB0           24
 #define AHB_GATE_OFFSET_MCTL           14
 #define AHB_GATE_OFFSET_GMAC           17
+#define AHB_GATE_OFFSET_NAND0          13
+#define AHB_GATE_OFFSET_NAND1          12
 #define AHB_GATE_OFFSET_MMC3           11
 #define AHB_GATE_OFFSET_MMC2           10
 #define AHB_GATE_OFFSET_MMC1           9
 #define AHB_GATE_OFFSET_MMC0           8
 #define AHB_GATE_OFFSET_MMC(n)         (AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_DMA            6
 #define AHB_GATE_OFFSET_SS             5
 
 /* ahb_gate1 offsets */
@@ -287,6 +290,7 @@ struct sunxi_ccm_reg {
 #define CCM_LCD_CH0_CTRL_GATE          (0x1 << 31)
 
 #define CCM_LCD_CH1_CTRL_M(n)          ((((n) - 1) & 0xf) << 0)
+#define CCM_LCD_CH1_CTRL_HALF_SCLK1    0 /* no seperate sclk1 & 2 on sun6i */
 #define CCM_LCD_CH1_CTRL_PLL3          (0 << 24)
 #define CCM_LCD_CH1_CTRL_PLL7          (1 << 24)
 #define CCM_LCD_CH1_CTRL_PLL3_2X       (2 << 24)
@@ -331,6 +335,9 @@ struct sunxi_ccm_reg {
 #define AHB_RESET_OFFSET_LCD1          5
 #define AHB_RESET_OFFSET_LCD0          4
 
+/* ahb_reset2 offsets */
+#define AHB_RESET_OFFSET_LVDS          0
+
 /* apb2 reset */
 #define APB2_RESET_UART_SHIFT          (16)
 #define APB2_RESET_UART_MASK           (0xff << APB2_RESET_UART_SHIFT)