Merge git://git.denx.de/u-boot-sunxi

[oweals/u-boot.git] / arch / arm / include / asm / arch-sunxi / clock_sun4i.h

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 01d3e28274fce0cc680acd574f4926a76d680fb9..d1c5ad0a739b55318f15ee7094f559b52319b718 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -208,6 +208,8 @@ struct sunxi_ccm_reg {
 #define CCM_AHB_GATE_DLL (0x1 << 15)
 #define CCM_AHB_GATE_ACE (0x1 << 16)
 
+#define CCM_PLL3_CTRL_M_SHIFT          0
+#define CCM_PLL3_CTRL_M_MASK           (0x7f << CCM_PLL3_CTRL_M_SHIFT)
 #define CCM_PLL3_CTRL_M(n)             (((n) & 0x7f) << 0)
 #define CCM_PLL3_CTRL_INTEGER_MODE     (0x1 << 15)
 #define CCM_PLL3_CTRL_EN               (0x1 << 31)
@@ -267,6 +269,11 @@ struct sunxi_ccm_reg {
 #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
 #define CCM_MBUS_CTRL_GATE (0x1 << 31)
 
+#define CCM_NAND_CTRL_M(x)             ((x) - 1)
+#define CCM_NAND_CTRL_N(x)             ((x) << 16)
+#define CCM_NAND_CTRL_OSCM24           (0x0 << 24)
+#define CCM_NAND_CTRL_PLL6             (0x1 << 24)
+#define CCM_NAND_CTRL_PLL5             (0x2 << 24)
 #define CCM_NAND_CTRL_ENABLE           (0x1 << 31)
 
 #define CCM_MMC_CTRL_M(x)              ((x) - 1)
@@ -287,11 +294,17 @@ struct sunxi_ccm_reg {
 #define CCM_LCD_CH0_CTRL_PLL7          (1 << 24)
 #define CCM_LCD_CH0_CTRL_PLL3_2X       (2 << 24)
 #define CCM_LCD_CH0_CTRL_PLL7_2X       (3 << 24)
+#define CCM_LCD_CH0_CTRL_MIPI_PLL      0 /* No mipi pll on sun4i/5i/7i */
+#ifdef CONFIG_MACH_SUN5I
+#define CCM_LCD_CH0_CTRL_TVE_RST       (0x1 << 29)
+#else
+#define CCM_LCD_CH0_CTRL_TVE_RST       0 /* No separate tve-rst on sun4i/7i */
+#endif
 #define CCM_LCD_CH0_CTRL_RST           (0x1 << 30)
 #define CCM_LCD_CH0_CTRL_GATE          (0x1 << 31)
 
 #define CCM_LCD_CH1_CTRL_M(n)          ((((n) - 1) & 0xf) << 0)
-/* We leave bit 11 set to 0, so sclk1 == sclk2 */
+#define CCM_LCD_CH1_CTRL_HALF_SCLK1    (1 << 11)
 #define CCM_LCD_CH1_CTRL_PLL3          (0 << 24)
 #define CCM_LCD_CH1_CTRL_PLL7          (1 << 24)
 #define CCM_LCD_CH1_CTRL_PLL3_2X       (2 << 24)
@@ -342,6 +355,7 @@ struct sunxi_ccm_reg {
 #ifndef __ASSEMBLY__
 void clock_set_pll1(unsigned int hz);
 void clock_set_pll3(unsigned int hz);
+unsigned int clock_get_pll3(void);
 unsigned int clock_get_pll5p(void);
 unsigned int clock_get_pll6(void);
 #endif