Merge tag 'dm-pull-29oct19' of git://git.denx.de/u-boot-dm

[oweals/u-boot.git] / arch / arm / include / asm / arch-sunxi / clock_sun4i.h

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index d297ed0f73e434cabcb1345e7c439bcb1639b70e..2cec91cb20e5dcb854b5177b6adae0faf2f86e4b 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -1,11 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * sun4i, sun5i and sun7i clock register definitions
  *
  * (C) Copyright 2007-2011
  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  * Tom Cubie <tangliang@allwinnertech.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _SUNXI_CLOCK_SUN4I_H
@@ -39,7 +38,7 @@ struct sunxi_ccm_reg {
        u32 apb0_gate;          /* 0x68 apb0 module clock gating */
        u32 apb1_gate;          /* 0x6c apb1 module clock gating */
        u8 res4[0x10];
-       u32 nand_sclk_cfg;      /* 0x80 nand sub clock control */
+       u32 nand0_clk_cfg;      /* 0x80 nand sub clock control */
        u32 ms_sclk_cfg;        /* 0x84 memory stick sub clock control */
        u32 sd0_clk_cfg;        /* 0x88 sd0 clock control */
        u32 sd1_clk_cfg;        /* 0x8c sd1 clock control */
@@ -144,7 +143,16 @@ struct sunxi_ccm_reg {
 
 #define PLL1_CFG_DEFAULT       0xa1005000
 
+#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
+/*
+ * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
+ * halving the mbus frequency, so set it to 300 MHz ourselves and base the
+ * mbus divider on that.
+ */
+#define PLL6_CFG_DEFAULT       0xa1009900
+#else
 #define PLL6_CFG_DEFAULT       0xa1009911
+#endif
 
 /* nand clock */
 #define NAND_CLK_SRC_OSC24             0
@@ -168,7 +176,7 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_ACE            16
 #define AHB_GATE_OFFSET_DLL            15
 #define AHB_GATE_OFFSET_SDRAM          14
-#define AHB_GATE_OFFSET_NAND           13
+#define AHB_GATE_OFFSET_NAND0          13
 #define AHB_GATE_OFFSET_MS             12
 #define AHB_GATE_OFFSET_MMC3           11
 #define AHB_GATE_OFFSET_MMC2           10
@@ -199,6 +207,8 @@ struct sunxi_ccm_reg {
 #define CCM_AHB_GATE_DLL (0x1 << 15)
 #define CCM_AHB_GATE_ACE (0x1 << 16)
 
+#define CCM_PLL3_CTRL_M_SHIFT          0
+#define CCM_PLL3_CTRL_M_MASK           (0x7f << CCM_PLL3_CTRL_M_SHIFT)
 #define CCM_PLL3_CTRL_M(n)             (((n) & 0x7f) << 0)
 #define CCM_PLL3_CTRL_INTEGER_MODE     (0x1 << 15)
 #define CCM_PLL3_CTRL_EN               (0x1 << 31)
@@ -258,6 +268,13 @@ struct sunxi_ccm_reg {
 #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
 #define CCM_MBUS_CTRL_GATE (0x1 << 31)
 
+#define CCM_NAND_CTRL_M(x)             ((x) - 1)
+#define CCM_NAND_CTRL_N(x)             ((x) << 16)
+#define CCM_NAND_CTRL_OSCM24           (0x0 << 24)
+#define CCM_NAND_CTRL_PLL6             (0x1 << 24)
+#define CCM_NAND_CTRL_PLL5             (0x2 << 24)
+#define CCM_NAND_CTRL_ENABLE           (0x1 << 31)
+
 #define CCM_MMC_CTRL_M(x)              ((x) - 1)
 #define CCM_MMC_CTRL_OCLK_DLY(x)       ((x) << 8)
 #define CCM_MMC_CTRL_N(x)              ((x) << 16)
@@ -276,11 +293,17 @@ struct sunxi_ccm_reg {
 #define CCM_LCD_CH0_CTRL_PLL7          (1 << 24)
 #define CCM_LCD_CH0_CTRL_PLL3_2X       (2 << 24)
 #define CCM_LCD_CH0_CTRL_PLL7_2X       (3 << 24)
+#define CCM_LCD_CH0_CTRL_MIPI_PLL      0 /* No mipi pll on sun4i/5i/7i */
+#ifdef CONFIG_MACH_SUN5I
+#define CCM_LCD_CH0_CTRL_TVE_RST       (0x1 << 29)
+#else
+#define CCM_LCD_CH0_CTRL_TVE_RST       0 /* No separate tve-rst on sun4i/7i */
+#endif
 #define CCM_LCD_CH0_CTRL_RST           (0x1 << 30)
 #define CCM_LCD_CH0_CTRL_GATE          (0x1 << 31)
 
 #define CCM_LCD_CH1_CTRL_M(n)          ((((n) - 1) & 0xf) << 0)
-/* We leave bit 11 set to 0, so sclk1 == sclk2 */
+#define CCM_LCD_CH1_CTRL_HALF_SCLK1    (1 << 11)
 #define CCM_LCD_CH1_CTRL_PLL3          (0 << 24)
 #define CCM_LCD_CH1_CTRL_PLL7          (1 << 24)
 #define CCM_LCD_CH1_CTRL_PLL3_2X       (2 << 24)
@@ -311,6 +334,8 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 6)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 7)
 #define CCM_USB_CTRL_PHYGATE (0x1 << 8)
 /* These 3 are sun6i only, define them as 0 on sun4i */
 #define CCM_USB_CTRL_PHY0_CLK 0
@@ -329,6 +354,7 @@ struct sunxi_ccm_reg {
 #ifndef __ASSEMBLY__
 void clock_set_pll1(unsigned int hz);
 void clock_set_pll3(unsigned int hz);
+unsigned int clock_get_pll3(void);
 unsigned int clock_get_pll5p(void);
 unsigned int clock_get_pll6(void);
 #endif