Merge git://git.denx.de/u-boot-mpc85xx

[oweals/u-boot.git] / arch / arm / include / asm / arch-stm32f7 / rcc.h

diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h
index 184c366d9d836ab72006803c279107596cd177f2..0f8d50b4c6140a11a3313bb2cd4f203166ef09c0 100644 (file)
--- a/arch/arm/include/asm/arch-stm32f7/rcc.h
+++ b/arch/arm/include/asm/arch-stm32f7/rcc.h
@@ -8,32 +8,6 @@
 #ifndef _STM32_RCC_H
 #define _STM32_RCC_H
 
-#define RCC_CR         0x00    /* clock control */
-#define RCC_PLLCFGR    0x04    /* PLL configuration */
-#define RCC_CFGR       0x08    /* clock configuration */
-#define RCC_CIR                0x0C    /* clock interrupt */
-#define RCC_AHB1RSTR   0x10    /* AHB1 peripheral reset */
-#define RCC_AHB2RSTR   0x14    /* AHB2 peripheral reset */
-#define RCC_AHB3RSTR   0x18    /* AHB3 peripheral reset */
-#define RCC_APB1RSTR   0x20    /* APB1 peripheral reset */
-#define RCC_APB2RSTR   0x24    /* APB2 peripheral reset */
-#define RCC_AHB1ENR    0x30    /* AHB1 peripheral clock enable */
-#define RCC_AHB2ENR    0x34    /* AHB2 peripheral clock enable */
-#define RCC_AHB3ENR    0x38    /* AHB3 peripheral clock enable */
-#define RCC_APB1ENR    0x40    /* APB1 peripheral clock enable */
-#define RCC_APB2ENR    0x44    /* APB2 peripheral clock enable */
-#define RCC_AHB1LPENR  0x50    /* periph clk enable in low pwr mode */
-#define RCC_AHB2LPENR  0x54    /* AHB2 periph clk enable in low pwr mode */
-#define RCC_AHB3LPENR  0x58    /* AHB3 periph clk enable in low pwr mode */
-#define RCC_APB1LPENR  0x60    /* APB1 periph clk enable in low pwr mode */
-#define RCC_APB2LPENR  0x64    /* APB2 periph clk enable in low pwr mode */
-#define RCC_BDCR       0x70    /* Backup domain control */
-#define RCC_CSR                0x74    /* clock control & status */
-#define RCC_SSCGR      0x80    /* spread spectrum clock generation */
-#define RCC_PLLI2SCFGR 0x84    /* PLLI2S configuration */
-#define RCC_PLLSAICFG  0x88    /* PLLSAI configuration */
-#define RCC_DCKCFG1    0x8C    /* dedicated clocks configuration register */
-#define RCC_DCKCFG2    0x90    /* dedicated clocks configuration register */
 /*
  * RCC AHB1ENR specific definitions
  */
@@ -57,6 +31,7 @@
  * RCC AHB3ENR specific definitions
  */
 #define RCC_AHB3ENR_FMC_EN             BIT(0)
+#define RCC_AHB3ENR_QSPI_EN             BIT(1)
 
 /*
  * RCC APB1ENR specific definitions