rockchip: pinctrl: rk3399: add GMAC (RGMII only) support

[oweals/u-boot.git] / arch / arm / include / asm / arch-rockchip / grf_rk3399.h

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index d3d1467ea46893bd7a6a4407854bf22cf9d58fbc..e709fdaad20a2a74acc55d4a3408b5b3b2e2a4b4 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -318,4 +318,159 @@ struct rk3399_pmusgrf_regs {
 };
 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
 
+enum {
+       /* GRF_GPIO2B_IOMUX */
+       GRF_GPIO2B1_SEL_SHIFT   = 0,
+       GRF_GPIO2B1_SEL_MASK    = 3 << GRF_GPIO2B1_SEL_SHIFT,
+       GRF_SPI2TPM_RXD         = 1,
+       GRF_GPIO2B2_SEL_SHIFT   = 2,
+       GRF_GPIO2B2_SEL_MASK    = 3 << GRF_GPIO2B2_SEL_SHIFT,
+       GRF_SPI2TPM_TXD         = 1,
+       GRF_GPIO2B3_SEL_SHIFT   = 6,
+       GRF_GPIO2B3_SEL_MASK    = 3 << GRF_GPIO2B3_SEL_SHIFT,
+       GRF_SPI2TPM_CLK         = 1,
+       GRF_GPIO2B4_SEL_SHIFT   = 8,
+       GRF_GPIO2B4_SEL_MASK    = 3 << GRF_GPIO2B4_SEL_SHIFT,
+       GRF_SPI2TPM_CSN0        = 1,
+
+       /* GRF_GPIO3A_IOMUX */
+       GRF_GPIO3A0_SEL_SHIFT   = 0,
+       GRF_GPIO3A0_SEL_MASK    = 3 << GRF_GPIO3A0_SEL_SHIFT,
+       GRF_MAC_TXD2            = 1,
+       GRF_GPIO3A1_SEL_SHIFT   = 2,
+       GRF_GPIO3A1_SEL_MASK    = 3 << GRF_GPIO3A1_SEL_SHIFT,
+       GRF_MAC_TXD3            = 1,
+       GRF_GPIO3A2_SEL_SHIFT   = 4,
+       GRF_GPIO3A2_SEL_MASK    = 3 << GRF_GPIO3A2_SEL_SHIFT,
+       GRF_MAC_RXD2            = 1,
+       GRF_GPIO3A3_SEL_SHIFT   = 6,
+       GRF_GPIO3A3_SEL_MASK    = 3 << GRF_GPIO3A3_SEL_SHIFT,
+       GRF_MAC_RXD3            = 1,
+       GRF_GPIO3A4_SEL_SHIFT   = 8,
+       GRF_GPIO3A4_SEL_MASK    = 3 << GRF_GPIO3A4_SEL_SHIFT,
+       GRF_MAC_TXD0            = 1,
+       GRF_SPI0NORCODEC_RXD    = 2,
+       GRF_GPIO3A5_SEL_SHIFT   = 10,
+       GRF_GPIO3A5_SEL_MASK    = 3 << GRF_GPIO3A5_SEL_SHIFT,
+       GRF_MAC_TXD1            = 1,
+       GRF_SPI0NORCODEC_TXD    = 2,
+       GRF_GPIO3A6_SEL_SHIFT   = 12,
+       GRF_GPIO3A6_SEL_MASK    = 3 << GRF_GPIO3A6_SEL_SHIFT,
+       GRF_MAC_RXD0            = 1,
+       GRF_SPI0NORCODEC_CLK    = 2,
+       GRF_GPIO3A7_SEL_SHIFT   = 14,
+       GRF_GPIO3A7_SEL_MASK    = 3 << GRF_GPIO3A7_SEL_SHIFT,
+       GRF_MAC_RXD1            = 1,
+       GRF_SPI0NORCODEC_CSN0   = 2,
+
+       /* GRF_GPIO3B_IOMUX */
+       GRF_GPIO3B0_SEL_SHIFT   = 0,
+       GRF_GPIO3B0_SEL_MASK    = 3 << GRF_GPIO3B0_SEL_SHIFT,
+       GRF_MAC_MDC             = 1,
+       GRF_SPI0NORCODEC_CSN1   = 2,
+       GRF_GPIO3B1_SEL_SHIFT   = 2,
+       GRF_GPIO3B1_SEL_MASK    = 3 << GRF_GPIO3B1_SEL_SHIFT,
+       GRF_MAC_RXDV            = 1,
+       GRF_GPIO3B3_SEL_SHIFT   = 6,
+       GRF_GPIO3B3_SEL_MASK    = 3 << GRF_GPIO3B3_SEL_SHIFT,
+       GRF_MAC_CLK             = 1,
+       GRF_GPIO3B4_SEL_SHIFT   = 8,
+       GRF_GPIO3B4_SEL_MASK    = 3 << GRF_GPIO3B4_SEL_SHIFT,
+       GRF_MAC_TXEN            = 1,
+       GRF_GPIO3B5_SEL_SHIFT   = 10,
+       GRF_GPIO3B5_SEL_MASK    = 3 << GRF_GPIO3B5_SEL_SHIFT,
+       GRF_MAC_MDIO            = 1,
+       GRF_GPIO3B6_SEL_SHIFT   = 12,
+       GRF_GPIO3B6_SEL_MASK    = 3 << GRF_GPIO3B6_SEL_SHIFT,
+       GRF_MAC_RXCLK           = 1,
+
+       /* GRF_GPIO3C_IOMUX */
+       GRF_GPIO3C1_SEL_SHIFT   = 2,
+       GRF_GPIO3C1_SEL_MASK    = 3 << GRF_GPIO3C1_SEL_SHIFT,
+       GRF_MAC_TXCLK           = 1,
+
+       /* GRF_GPIO4B_IOMUX */
+       GRF_GPIO4B0_SEL_SHIFT   = 0,
+       GRF_GPIO4B0_SEL_MASK    = 3 << GRF_GPIO4B0_SEL_SHIFT,
+       GRF_SDMMC_DATA0         = 1,
+       GRF_UART2DBGA_SIN       = 2,
+       GRF_GPIO4B1_SEL_SHIFT   = 2,
+       GRF_GPIO4B1_SEL_MASK    = 3 << GRF_GPIO4B1_SEL_SHIFT,
+       GRF_SDMMC_DATA1         = 1,
+       GRF_UART2DBGA_SOUT      = 2,
+       GRF_GPIO4B2_SEL_SHIFT   = 4,
+       GRF_GPIO4B2_SEL_MASK    = 3 << GRF_GPIO4B2_SEL_SHIFT,
+       GRF_SDMMC_DATA2         = 1,
+       GRF_GPIO4B3_SEL_SHIFT   = 6,
+       GRF_GPIO4B3_SEL_MASK    = 3 << GRF_GPIO4B3_SEL_SHIFT,
+       GRF_SDMMC_DATA3         = 1,
+       GRF_GPIO4B4_SEL_SHIFT   = 8,
+       GRF_GPIO4B4_SEL_MASK    = 3 << GRF_GPIO4B4_SEL_SHIFT,
+       GRF_SDMMC_CLKOUT        = 1,
+       GRF_GPIO4B5_SEL_SHIFT   = 10,
+       GRF_GPIO4B5_SEL_MASK    = 3 << GRF_GPIO4B5_SEL_SHIFT,
+       GRF_SDMMC_CMD           = 1,
+
+       /*  GRF_GPIO4C_IOMUX */
+       GRF_GPIO4C0_SEL_SHIFT   = 0,
+       GRF_GPIO4C0_SEL_MASK    = 3 << GRF_GPIO4C0_SEL_SHIFT,
+       GRF_UART2DGBB_SIN       = 2,
+       GRF_GPIO4C1_SEL_SHIFT   = 2,
+       GRF_GPIO4C1_SEL_MASK    = 3 << GRF_GPIO4C1_SEL_SHIFT,
+       GRF_UART2DGBB_SOUT      = 2,
+       GRF_GPIO4C2_SEL_SHIFT   = 4,
+       GRF_GPIO4C2_SEL_MASK    = 3 << GRF_GPIO4C2_SEL_SHIFT,
+       GRF_PWM_0               = 1,
+       GRF_GPIO4C3_SEL_SHIFT   = 6,
+       GRF_GPIO4C3_SEL_MASK    = 3 << GRF_GPIO4C3_SEL_SHIFT,
+       GRF_UART2DGBC_SIN       = 1,
+       GRF_GPIO4C4_SEL_SHIFT   = 8,
+       GRF_GPIO4C4_SEL_MASK    = 3 << GRF_GPIO4C4_SEL_SHIFT,
+       GRF_UART2DBGC_SOUT      = 1,
+       GRF_GPIO4C6_SEL_SHIFT   = 12,
+       GRF_GPIO4C6_SEL_MASK    = 3 << GRF_GPIO4C6_SEL_SHIFT,
+       GRF_PWM_1               = 1,
+
+       /* GRF_SOC_CON7 */
+       GRF_UART_DBG_SEL_SHIFT  = 10,
+       GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
+       GRF_UART_DBG_SEL_C      = 2,
+
+       /*  PMUGRF_GPIO0A_IOMUX */
+       PMUGRF_GPIO0A6_SEL_SHIFT        = 12,
+       PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
+       PMUGRF_PWM_3A           = 1,
+
+       /*  PMUGRF_GPIO1A_IOMUX */
+       PMUGRF_GPIO1A7_SEL_SHIFT        = 14,
+       PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
+       PMUGRF_SPI1EC_RXD       = 2,
+
+       /*  PMUGRF_GPIO1B_IOMUX */
+       PMUGRF_GPIO1B0_SEL_SHIFT        = 0,
+       PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
+       PMUGRF_SPI1EC_TXD       = 2,
+       PMUGRF_GPIO1B1_SEL_SHIFT        = 2,
+       PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
+       PMUGRF_SPI1EC_CLK       = 2,
+       PMUGRF_GPIO1B2_SEL_SHIFT        = 4,
+       PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
+       PMUGRF_SPI1EC_CSN0      = 2,
+       PMUGRF_GPIO1B6_SEL_SHIFT        = 12,
+       PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
+       PMUGRF_PWM_3B           = 1,
+       PMUGRF_GPIO1B7_SEL_SHIFT        = 14,
+       PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
+       PMUGRF_I2C0PMU_SDA      = 2,
+
+       /*  PMUGRF_GPIO1C_IOMUX */
+       PMUGRF_GPIO1C0_SEL_SHIFT        = 0,
+       PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
+       PMUGRF_I2C0PMU_SCL      = 2,
+       PMUGRF_GPIO1C3_SEL_SHIFT        = 6,
+       PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
+       PMUGRF_PWM_2            = 1,
+
+};
+
 #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */