rockchip: rk322x: add clock driver

[oweals/u-boot.git] / arch / arm / include / asm / arch-rockchip / grf_rk3399.h

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index b340b05e36e995871d164f8ce1c50bf4895d34fe..8d21eb7bee7230a45d122a9916e977a665ac7ea0 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -151,10 +151,11 @@ struct rk3399_grf_regs {
        u32 gpio2_sr[3][4];
        u32 reserved23[4];
        u32 gpio2_smt[3][4];
-       u32 reserved24[(0xe130 - 0xe0ec)/4 - 1];
-       u32 gpio4b_e01;
-       u32 gpio4b_e2;
-       u32 reserved24a[(0xe200 - 0xe134)/4 - 1];
+       u32 reserved24[(0xe100 - 0xe0ec)/4 - 1];
+       u32 gpio2_e[4];
+       u32 gpio3_e[7];
+       u32 gpio4_e[5];
+       u32 reserved24a[(0xe200 - 0xe13c)/4 - 1];
        u32 soc_con0;
        u32 soc_con1;
        u32 soc_con2;
@@ -337,6 +338,26 @@ enum {
        GRF_GPIO2B4_SEL_MASK    = 3 << GRF_GPIO2B4_SEL_SHIFT,
        GRF_SPI2TPM_CSN0        = 1,
 
+       /* GRF_GPIO2C_IOMUX */
+       GRF_GPIO2C0_SEL_SHIFT   = 0,
+       GRF_GPIO2C0_SEL_MASK    = 3 << GRF_GPIO2C0_SEL_SHIFT,
+       GRF_UART0BT_SIN         = 1,
+       GRF_GPIO2C1_SEL_SHIFT   = 2,
+       GRF_GPIO2C1_SEL_MASK    = 3 << GRF_GPIO2C1_SEL_SHIFT,
+       GRF_UART0BT_SOUT        = 1,
+       GRF_GPIO2C4_SEL_SHIFT   = 8,
+       GRF_GPIO2C4_SEL_MASK    = 3 << GRF_GPIO2C4_SEL_SHIFT,
+       GRF_SPI5EXPPLUS_RXD     = 2,
+       GRF_GPIO2C5_SEL_SHIFT   = 10,
+       GRF_GPIO2C5_SEL_MASK    = 3 << GRF_GPIO2C5_SEL_SHIFT,
+       GRF_SPI5EXPPLUS_TXD     = 2,
+       GRF_GPIO2C6_SEL_SHIFT   = 12,
+       GRF_GPIO2C6_SEL_MASK    = 3 << GRF_GPIO2C6_SEL_SHIFT,
+       GRF_SPI5EXPPLUS_CLK     = 2,
+       GRF_GPIO2C7_SEL_SHIFT   = 14,
+       GRF_GPIO2C7_SEL_MASK    = 3 << GRF_GPIO2C7_SEL_SHIFT,
+       GRF_SPI5EXPPLUS_CSN0    = 2,
+
        /* GRF_GPIO3A_IOMUX */
        GRF_GPIO3A0_SEL_SHIFT   = 0,
        GRF_GPIO3A0_SEL_MASK    = 3 << GRF_GPIO3A0_SEL_SHIFT,
@@ -419,9 +440,11 @@ enum {
        GRF_GPIO4C0_SEL_SHIFT   = 0,
        GRF_GPIO4C0_SEL_MASK    = 3 << GRF_GPIO4C0_SEL_SHIFT,
        GRF_UART2DGBB_SIN       = 2,
+       GRF_HDMII2C_SCL         = 3,
        GRF_GPIO4C1_SEL_SHIFT   = 2,
        GRF_GPIO4C1_SEL_MASK    = 3 << GRF_GPIO4C1_SEL_SHIFT,
        GRF_UART2DGBB_SOUT      = 2,
+       GRF_HDMII2C_SDA         = 3,
        GRF_GPIO4C2_SEL_SHIFT   = 4,
        GRF_GPIO4C2_SEL_MASK    = 3 << GRF_GPIO4C2_SEL_SHIFT,
        GRF_PWM_0               = 1,
@@ -435,10 +458,102 @@ enum {
        GRF_GPIO4C6_SEL_MASK    = 3 << GRF_GPIO4C6_SEL_SHIFT,
        GRF_PWM_1               = 1,
 
+       /* GRF_GPIO3A_E01 */
+       GRF_GPIO3A0_E_SHIFT = 0,
+       GRF_GPIO3A0_E_MASK = 7 << GRF_GPIO3A0_E_SHIFT,
+       GRF_GPIO3A1_E_SHIFT = 3,
+       GRF_GPIO3A1_E_MASK = 7 << GRF_GPIO3A1_E_SHIFT,
+       GRF_GPIO3A2_E_SHIFT = 6,
+       GRF_GPIO3A2_E_MASK = 7 << GRF_GPIO3A2_E_SHIFT,
+       GRF_GPIO3A3_E_SHIFT = 9,
+       GRF_GPIO3A3_E_MASK = 7 << GRF_GPIO3A3_E_SHIFT,
+       GRF_GPIO3A4_E_SHIFT = 12,
+       GRF_GPIO3A4_E_MASK = 7 << GRF_GPIO3A4_E_SHIFT,
+       GRF_GPIO3A5_E0_SHIFT = 15,
+       GRF_GPIO3A5_E0_MASK = 1 << GRF_GPIO3A5_E0_SHIFT,
+
+       /*  GRF_GPIO3A_E2 */
+       GRF_GPIO3A5_E12_SHIFT = 0,
+       GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT,
+       GRF_GPIO3A6_E_SHIFT = 2,
+       GRF_GPIO3A6_E_MASK = 7 << GRF_GPIO3A6_E_SHIFT,
+       GRF_GPIO3A7_E_SHIFT = 5,
+       GRF_GPIO3A7_E_MASK = 7 << GRF_GPIO3A7_E_SHIFT,
+
+       /* GRF_GPIO3B_E01 */
+       GRF_GPIO3B0_E_SHIFT = 0,
+       GRF_GPIO3B0_E_MASK = 7 << GRF_GPIO3B0_E_SHIFT,
+       GRF_GPIO3B1_E_SHIFT = 3,
+       GRF_GPIO3B1_E_MASK = 7 << GRF_GPIO3B1_E_SHIFT,
+       GRF_GPIO3B2_E_SHIFT = 6,
+       GRF_GPIO3B2_E_MASK = 7 << GRF_GPIO3B2_E_SHIFT,
+       GRF_GPIO3B3_E_SHIFT = 9,
+       GRF_GPIO3B3_E_MASK = 7 << GRF_GPIO3B3_E_SHIFT,
+       GRF_GPIO3B4_E_SHIFT = 12,
+       GRF_GPIO3B4_E_MASK = 7 << GRF_GPIO3B4_E_SHIFT,
+       GRF_GPIO3B5_E0_SHIFT = 15,
+       GRF_GPIO3B5_E0_MASK = 1 << GRF_GPIO3B5_E0_SHIFT,
+
+       /*  GRF_GPIO3A_E2 */
+       GRF_GPIO3B5_E12_SHIFT = 0,
+       GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT,
+       GRF_GPIO3B6_E_SHIFT = 2,
+       GRF_GPIO3B6_E_MASK = 7 << GRF_GPIO3B6_E_SHIFT,
+       GRF_GPIO3B7_E_SHIFT = 5,
+       GRF_GPIO3B7_E_MASK = 7 << GRF_GPIO3B7_E_SHIFT,
+
+       /* GRF_GPIO3C_E01 */
+       GRF_GPIO3C0_E_SHIFT = 0,
+       GRF_GPIO3C0_E_MASK = 7 << GRF_GPIO3C0_E_SHIFT,
+       GRF_GPIO3C1_E_SHIFT = 3,
+       GRF_GPIO3C1_E_MASK = 7 << GRF_GPIO3C1_E_SHIFT,
+       GRF_GPIO3C2_E_SHIFT = 6,
+       GRF_GPIO3C2_E_MASK = 7 << GRF_GPIO3C2_E_SHIFT,
+       GRF_GPIO3C3_E_SHIFT = 9,
+       GRF_GPIO3C3_E_MASK = 7 << GRF_GPIO3C3_E_SHIFT,
+       GRF_GPIO3C4_E_SHIFT = 12,
+       GRF_GPIO3C4_E_MASK = 7 << GRF_GPIO3C4_E_SHIFT,
+       GRF_GPIO3C5_E0_SHIFT = 15,
+       GRF_GPIO3C5_E0_MASK = 1 << GRF_GPIO3C5_E0_SHIFT,
+
+       /*  GRF_GPIO3C_E2 */
+       GRF_GPIO3C5_E12_SHIFT = 0,
+       GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT,
+       GRF_GPIO3C6_E_SHIFT = 2,
+       GRF_GPIO3C6_E_MASK = 7 << GRF_GPIO3C6_E_SHIFT,
+       GRF_GPIO3C7_E_SHIFT = 5,
+       GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT,
+
        /* GRF_SOC_CON7 */
-       GRF_UART_DBG_SEL_SHIFT  = 10,
-       GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
-       GRF_UART_DBG_SEL_C      = 2,
+       GRF_UART_DBG_SEL_SHIFT  = 10,
+       GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
+       GRF_UART_DBG_SEL_C      = 2,
+
+       /* GRF_SOC_CON20 */
+       GRF_DSI0_VOP_SEL_SHIFT  = 0,
+       GRF_DSI0_VOP_SEL_MASK   = 1 << GRF_DSI0_VOP_SEL_SHIFT,
+       GRF_DSI0_VOP_SEL_B      = 0,
+       GRF_DSI0_VOP_SEL_L      = 1,
+       GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6,
+       GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6,
+       GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6,
+
+       /* GRF_SOC_CON22 */
+       GRF_DPHY_TX0_RXMODE_SHIFT = 0,
+       GRF_DPHY_TX0_RXMODE_MASK  = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
+       GRF_DPHY_TX0_RXMODE_EN    = 0xb,
+       GRF_DPHY_TX0_RXMODE_DIS   = 0,
+
+       GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
+       GRF_DPHY_TX0_TXSTOPMODE_MASK  = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
+       GRF_DPHY_TX0_TXSTOPMODE_EN    = 0xc,
+       GRF_DPHY_TX0_TXSTOPMODE_DIS   = 0,
+
+       GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
+       GRF_DPHY_TX0_TURNREQUEST_MASK  =
+               0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
+       GRF_DPHY_TX0_TURNREQUEST_EN    = 0x1,
+       GRF_DPHY_TX0_TURNREQUEST_DIS   = 0,
 
        /*  PMUGRF_GPIO0A_IOMUX */
        PMUGRF_GPIO0A6_SEL_SHIFT        = 12,