rockchip: rk3036: fix grf macro define

[oweals/u-boot.git] / arch / arm / include / asm / arch-rockchip / grf_rk3288.h

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index 7d56b8ced0a916c21d1a95667ef2ca83ed1632bc..818e4c5666147c179ee0d807ba5f88ab0d72c286 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -283,6 +283,163 @@ enum {
        GPIO3C0_EMMC_CMD,
 };
 
+/* GRF_GPIO3DL_IOMUX */
+enum {
+       GPIO3D3_SHIFT           = 12,
+       GPIO3D3_MASK            = 7,
+       GPIO3D3_GPIO            = 0,
+       GPIO3D3_FLASH1_DATA3,
+       GPIO3D3_HOST_DOUT3,
+       GPIO3D3_MAC_RXD3,
+       GPIO3D3_SDIO1_DATA3,
+
+       GPIO3D2_SHIFT           = 8,
+       GPIO3D2_MASK            = 7,
+       GPIO3D2_GPIO            = 0,
+       GPIO3D2_FLASH1_DATA2,
+       GPIO3D2_HOST_DOUT2,
+       GPIO3D2_MAC_RXD2,
+       GPIO3D2_SDIO1_DATA2,
+
+       GPIO3D1_SHIFT           = 4,
+       GPIO3D1_MASK            = 7,
+       GPIO3D1_GPIO            = 0,
+       GPIO3DL1_FLASH1_DATA1,
+       GPIO3D1_HOST_DOUT1,
+       GPIO3D1_MAC_TXD3,
+       GPIO3D1_SDIO1_DATA1,
+
+       GPIO3D0_SHIFT           = 0,
+       GPIO3D0_MASK            = 7,
+       GPIO3D0_GPIO            = 0,
+       GPIO3D0_FLASH1_DATA0,
+       GPIO3D0_HOST_DOUT0,
+       GPIO3D0_MAC_TXD2,
+       GPIO3D0_SDIO1_DATA0,
+};
+
+/* GRF_GPIO3HL_IOMUX */
+enum {
+       GPIO3D7_SHIFT           = 12,
+       GPIO3D7_MASK            = 7,
+       GPIO3D7_GPIO            = 0,
+       GPIO3D7_FLASH1_DATA7,
+       GPIO3D7_HOST_DOUT7,
+       GPIO3D7_MAC_RXD1,
+       GPIO3D7_SDIO1_INTN,
+
+       GPIO3D6_SHIFT           = 8,
+       GPIO3D6_MASK            = 7,
+       GPIO3D6_GPIO            = 0,
+       GPIO3D6_FLASH1_DATA6,
+       GPIO3D6_HOST_DOUT6,
+       GPIO3D6_MAC_RXD0,
+       GPIO3D6_SDIO1_BKPWR,
+
+       GPIO3D5_SHIFT           = 4,
+       GPIO3D5_MASK            = 7,
+       GPIO3D5_GPIO            = 0,
+       GPIO3D5_FLASH1_DATA5,
+       GPIO3D5_HOST_DOUT5,
+       GPIO3D5_MAC_TXD1,
+       GPIO3D5_SDIO1_WRPRT,
+
+       GPIO3D4_SHIFT           = 0,
+       GPIO3D4_MASK            = 7,
+       GPIO3D4_GPIO            = 0,
+       GPIO3D4_FLASH1_DATA4,
+       GPIO3D4_HOST_DOUT4,
+       GPIO3D4_MAC_TXD0,
+       GPIO3D4_SDIO1_DETECTN,
+};
+
+/* GRF_GPIO4AL_IOMUX */
+enum {
+       GPIO4A3_SHIFT           = 12,
+       GPIO4A3_MASK            = 7,
+       GPIO4A3_GPIO            = 0,
+       GPIO4A3_FLASH1_ALE,
+       GPIO4A3_HOST_DOUT9,
+       GPIO4A3_MAC_CLK,
+       GPIO4A3_FLASH0_CSN6,
+
+       GPIO4A2_SHIFT           = 8,
+       GPIO4A2_MASK            = 7,
+       GPIO4A2_GPIO            = 0,
+       GPIO4A2_FLASH1_RDN,
+       GPIO4A2_HOST_DOUT8,
+       GPIO4A2_MAC_RXER,
+       GPIO4A2_FLASH0_CSN5,
+
+       GPIO4A1_SHIFT           = 4,
+       GPIO4A1_MASK            = 7,
+       GPIO4A1_GPIO            = 0,
+       GPIO4A1_FLASH1_WP,
+       GPIO4A1_HOST_CKOUTN,
+       GPIO4A1_MAC_TXDV,
+       GPIO4A1_FLASH0_CSN4,
+
+       GPIO4A0_SHIFT           = 0,
+       GPIO4A0_MASK            = 3,
+       GPIO4A0_GPIO            = 0,
+       GPIO4A0_FLASH1_RDY,
+       GPIO4A0_HOST_CKOUTP,
+       GPIO4A0_MAC_MDC,
+};
+
+/* GRF_GPIO4AH_IOMUX */
+enum {
+       GPIO4A7_SHIFT           = 12,
+       GPIO4A7_MASK            = 7,
+       GPIO4A7_GPIO            = 0,
+       GPIO4A7_FLASH1_CSN1,
+       GPIO4A7_HOST_DOUT13,
+       GPIO4A7_MAC_CSR,
+       GPIO4A7_SDIO1_CLKOUT,
+
+       GPIO4A6_SHIFT           = 8,
+       GPIO4A6_MASK            = 7,
+       GPIO4A6_GPIO            = 0,
+       GPIO4A6_FLASH1_CSN0,
+       GPIO4A6_HOST_DOUT12,
+       GPIO4A6_MAC_RXCLK,
+       GPIO4A6_SDIO1_CMD,
+
+       GPIO4A5_SHIFT           = 4,
+       GPIO4A5_MASK            = 3,
+       GPIO4A5_GPIO            = 0,
+       GPIO4A5_FLASH1_WRN,
+       GPIO4A5_HOST_DOUT11,
+       GPIO4A5_MAC_MDIO,
+
+       GPIO4A4_SHIFT           = 0,
+       GPIO4A4_MASK            = 7,
+       GPIO4A4_GPIO            = 0,
+       GPIO4A4_FLASH1_CLE,
+       GPIO4A4_HOST_DOUT10,
+       GPIO4A4_MAC_TXEN,
+       GPIO4A4_FLASH0_CSN7,
+};
+
+/* GRF_GPIO4BL_IOMUX */
+enum {
+       GPIO4B1_SHIFT           = 4,
+       GPIO4B1_MASK            = 7,
+       GPIO4B1_GPIO            = 0,
+       GPIO4B1_FLASH1_CSN2,
+       GPIO4B1_HOST_DOUT15,
+       GPIO4B1_MAC_TXCLK,
+       GPIO4B1_SDIO1_PWREN,
+
+       GPIO4B0_SHIFT           = 0,
+       GPIO4B0_MASK            = 7,
+       GPIO4B0_GPIO            = 0,
+       GPIO4B0_FLASH1_DQS,
+       GPIO4B0_HOST_DOUT14,
+       GPIO4B0_MAC_COL,
+       GPIO4B0_FLASH1_CSN3,
+};
+
 /* GRF_GPIO4C_IOMUX */
 enum {
        GPIO4C7_SHIFT           = 14,
@@ -813,7 +970,7 @@ enum {
                (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
        RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
        RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
-               (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+               (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
 
        RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
        RK3288_CLK_RX_DL_CFG_GMAC_MASK =
@@ -886,4 +1043,25 @@ enum GRF_SOC_CON8 {
        RK3288_DPHY_TX0_TURNREQUEST_DIS = 0,
 };
 
+/* GPIO Bias settings */
+enum GPIO_BIAS {
+       GPIO_BIAS_2MA = 0,
+       GPIO_BIAS_4MA,
+       GPIO_BIAS_8MA,
+       GPIO_BIAS_12MA,
+};
+
+#define GPIO_BIAS_MASK 0x3
+#define GPIO_BIAS_SHIFT(x)  ((x) * 2)
+
+enum GPIO_PU_PD {
+       GPIO_PULL_NORMAL = 0,
+       GPIO_PULL_UP,
+       GPIO_PULL_DOWN,
+       GPIO_PULL_REPEAT,
+};
+
+#define GPIO_PULL_MASK 0x3
+#define GPIO_PULL_SHIFT(x)  ((x) * 2)
+
 #endif