rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ

[oweals/u-boot.git] / arch / arm / include / asm / arch-rockchip / ddr_rk3288.h

diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
index fccabcd2c03e30baf38ce2292ad5a43d883e52f8..35696c741ff3c4804ed784ca72175bff2d94f635 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
@@ -425,6 +425,14 @@ enum {
 
 #define START_CMD                      (1u << 31)
 
+/*
+ * DDRCONF
+ * [5:4] row(13+n)
+ * [1:0] col(9+n), assume bw=2
+ */
+#define DDRCONF_ROW_SHIFT              4
+#define DDRCONF_COL_SHIFT              0
+
 /* DEVTODEV */
 #define BUSWRTORD_SHIFT                        4
 #define BUSRDTOWR_SHIFT                        2
@@ -433,52 +441,4 @@ enum {
 /* mr1 for ddr3 */
 #define DDR3_DLL_DISABLE               1
 
-/*
- *TODO(sjg@chromium.org): We use a PMU register to store SDRAM information for
- * passing from SPL to U-Boot. It would probably be better to use a normal C
- * structure in SRAM.
- *
- * sys_reg bitfield struct
- * [31] row_3_4_ch1
- * [30] row_3_4_ch0
- * [29:28] chinfo
- * [27] rank_ch1
- * [26:25] col_ch1
- * [24] bk_ch1
- * [23:22] cs0_row_ch1
- * [21:20] cs1_row_ch1
- * [19:18] bw_ch1
- * [17:16] dbw_ch1;
- * [15:13] ddrtype
- * [12] channelnum
- * [11] rank_ch0
- * [10:9] col_ch0
- * [8] bk_ch0
- * [7:6] cs0_row_ch0
- * [5:4] cs1_row_ch0
- * [3:2] bw_ch0
- * [1:0] dbw_ch0
-*/
-#define SYS_REG_DDRTYPE_SHIFT          13
-#define SYS_REG_DDRTYPE_MASK           7
-#define SYS_REG_NUM_CH_SHIFT           12
-#define SYS_REG_NUM_CH_MASK            1
-#define SYS_REG_ROW_3_4_SHIFT(ch)      (30 + (ch))
-#define SYS_REG_ROW_3_4_MASK           1
-#define SYS_REG_CHINFO_SHIFT(ch)       (28 + (ch))
-#define SYS_REG_RANK_SHIFT(ch)         (11 + (ch) * 16)
-#define SYS_REG_RANK_MASK              1
-#define SYS_REG_COL_SHIFT(ch)          (9 + (ch) * 16)
-#define SYS_REG_COL_MASK               3
-#define SYS_REG_BK_SHIFT(ch)           (8 + (ch) * 16)
-#define SYS_REG_BK_MASK                        1
-#define SYS_REG_CS0_ROW_SHIFT(ch)      (6 + (ch) * 16)
-#define SYS_REG_CS0_ROW_MASK           3
-#define SYS_REG_CS1_ROW_SHIFT(ch)      (4 + (ch) * 16)
-#define SYS_REG_CS1_ROW_MASK           3
-#define SYS_REG_BW_SHIFT(ch)           (2 + (ch) * 16)
-#define SYS_REG_BW_MASK                        3
-#define SYS_REG_DBW_SHIFT(ch)          ((ch) * 16)
-#define SYS_REG_DBW_MASK               3
-
 #endif