Merge git://git.denx.de/u-boot-dm

[oweals/u-boot.git] / arch / arm / include / asm / arch-rockchip / clock.h

diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 2e5ba86a633895c826e5c8e03fc1669c704dd589..641df58ac258b00730fdda72312c36ba03cc55a3 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -16,6 +16,10 @@ enum {
        ROCKCHIP_SYSCON_GRF,
        ROCKCHIP_SYSCON_SGRF,
        ROCKCHIP_SYSCON_PMU,
+       ROCKCHIP_SYSCON_PMUGRF,
+       ROCKCHIP_SYSCON_PMUSGRF,
+       ROCKCHIP_SYSCON_CIC,
+       ROCKCHIP_SYSCON_MSCH,
 };
 
 /* Standard Rockchip clock numbers */
@@ -35,6 +39,26 @@ static inline int rk_pll_id(enum rk_clk_id clk_id)
        return clk_id - 1;
 }
 
+/**
+ * clk_get_divisor() - Calculate the required clock divisior
+ *
+ * Given an input rate and a required output_rate, calculate the Rockchip
+ * divisor needed to achieve this.
+ *
+ * @input_rate:                Input clock rate in Hz
+ * @output_rate:       Output clock rate in Hz
+ * @return divisor register value to use
+ */
+static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
+{
+       uint clk_div;
+
+       clk_div = input_rate / output_rate;
+       clk_div = (clk_div + 1) & 0xfffe;
+
+       return clk_div;
+}
+
 /**
  * rockchip_get_cru() - get a pointer to the clock/reset unit registers
  *
@@ -42,4 +66,18 @@ static inline int rk_pll_id(enum rk_clk_id clk_id)
  */
 void *rockchip_get_cru(void);
 
+/**
+ * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
+ *
+ * @return pointer to registers, or -ve error on error
+ */
+void *rockchip_get_pmucru(void);
+
+struct rk3288_cru;
+struct rk3288_grf;
+
+void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
+
+int rockchip_get_clk(struct udevice **devp);
+
 #endif