Merge branch 'master' of git://git.denx.de/u-boot-blackfin

[oweals/u-boot.git] / arch / arm / include / asm / arch-rmobile / rcar-base.h

diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index 4331d3137c0e96456576d2560b348fbbf0837571..d594cd77c176532a79fb5629369ed72886bd476c 100644 (file)
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -10,7 +10,7 @@
 #define __ASM_ARCH_RCAR_BASE_H
 
 /*
- * R-Car (R8A7790/R8A7791) I/O Addresses
+ * R-Car (R8A7790/R8A7791/R8A7793/R8A7794) I/O Addresses
  */
 #define RWDT_BASE              0xE6020000
 #define SWDT_BASE              0xE6030000
@@ -21,6 +21,70 @@
 #define GPIO5_BASE             0xE6055000
 #define SH_QSPI_BASE           0xE6B10000
 
+/* SCIF */
+#define SCIF0_BASE             0xE6E60000
+#define SCIF1_BASE             0xE6E68000
+#define SCIF2_BASE             0xE6E58000
+#define SCIF3_BASE             0xE6EA8000
+#define SCIF4_BASE             0xE6EE0000
+#define SCIF5_BASE             0xE6EE8000
+
+/* Module stop status register */
+#define MSTPSR0                        0xE6150030
+#define MSTPSR1                        0xE6150038
+#define MSTPSR2                        0xE6150040
+#define MSTPSR3                        0xE6150048
+#define MSTPSR4                        0xE615004C
+#define MSTPSR5                        0xE615003C
+#define MSTPSR7                        0xE61501C4
+#define MSTPSR8                        0xE61509A0
+#define MSTPSR9                        0xE61509A4
+#define MSTPSR10               0xE61509A8
+#define MSTPSR11               0xE61509AC
+
+/* Realtime module stop control register */
+#define RMSTPCR0               0xE6150110
+#define RMSTPCR1               0xE6150114
+#define RMSTPCR2               0xE6150118
+#define RMSTPCR3               0xE615011C
+#define RMSTPCR4               0xE6150120
+#define RMSTPCR5               0xE6150124
+#define RMSTPCR7               0xE615012C
+#define RMSTPCR8               0xE6150980
+#define RMSTPCR9               0xE6150984
+#define RMSTPCR10              0xE6150988
+#define RMSTPCR11              0xE615098C
+
+/* System module stop control register */
+#define SMSTPCR0               0xE6150130
+#define SMSTPCR1               0xE6150134
+#define SMSTPCR2               0xE6150138
+#define SMSTPCR3               0xE615013C
+#define SMSTPCR4               0xE6150140
+#define SMSTPCR5               0xE6150144
+#define SMSTPCR7               0xE615014C
+#define SMSTPCR8               0xE6150990
+#define SMSTPCR9               0xE6150994
+#define SMSTPCR10              0xE6150998
+#define SMSTPCR11              0xE615099C
+
+/*
+ * SH-I2C
+ * Ch2 and ch3 are different address. These are defined
+ * in the header of each SoCs.
+ */
+#define CONFIG_SYS_I2C_SH_BASE0        0xE6500000
+#define CONFIG_SYS_I2C_SH_BASE1        0xE6510000
+
+/* RCAR-I2C */
+#define CONFIG_SYS_RCAR_I2C0_BASE      0xE6508000
+#define CONFIG_SYS_RCAR_I2C1_BASE      0xE6518000
+#define CONFIG_SYS_RCAR_I2C2_BASE      0xE6530000
+#define CONFIG_SYS_RCAR_I2C3_BASE      0xE6540000
+
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI0_BASE       0xEE100000
+
 #define S3C_BASE               0xE6784000
 #define S3C_INT_BASE           0xE6784A00
 #define S3C_MEDIA_BASE         0xE6784B00
@@ -108,7 +172,7 @@
 #define SYS_AXI_SAT1_BASE      0xFF8009C0
 #define SYS_AXI_SDM0_BASE      0xFF800A00
 #define SYS_AXI_SDM1_BASE      0xFF800A40
-#define SYS_AXI_TRAB_BASE      0xFF800B00
+#define SYS_AXI_TRAB_BASE      0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
 #define SYS_AXI_UDM0_BASE      0xFF800B80
 #define SYS_AXI_UDM1_BASE      0xFF800BC0
 
@@ -377,6 +441,8 @@
 #define PLL0CR                 0xE61500D8
 #define PLL0_STC_MASK          0x7F000000
 #define PLL0_STC_BIT           24
+#define PLLECR                 0xE61500D0
+#define PLL0ST                 0x100
 
 #ifndef __ASSEMBLY__
 #include <asm/types.h>