#define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */
#define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */
#define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */
#define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */
#define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */
#define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */
#define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */
#define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
#define DCSR(x) (0x40000000 | ((x) << 2))
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
-#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
/*
* USB Device Controller
*/
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define UDCCR 0x40600000 /* UDC Control Register */
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge Interrupt Enable */
#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */
-#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
+#define UDCCSN(x) (0x40600100 + ((x) << 2))
#define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
#define UDCCSR_PC (1 << 1) /* Packet Complete */
#define UDCCSR_FS (1 << 0) /* FIFO needs service */
-#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
+#define UDCBCN(x) (0x40600200 + ((x) << 2))
#define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */
#define UDCBCRA 0x40600204 /* Byte Count Register - EPA */
#define UDCBCRB 0x40600208 /* Byte Count Register - EPB */
#define UDCBCRW 0x40600258 /* Byte Count Register - EPW */
#define UDCBCRX 0x4060025C /* Byte Count Register - EPX */
-#define UDCDN(x) __REG2(0x40600300, (x)<<2)
+#define UDCDN(x) (0x40600300 + ((x) << 2))
#define UDCDR0 0x40600300 /* Data Register - EP0 */
#define UDCDRA 0x40600304 /* Data Register - EPA */
#define UDCDRB 0x40600308 /* Data Register - EPB */
#define UDCDRW 0x40600358 /* Data Register - EPW */
#define UDCDRX 0x4060035C /* Data Register - EPX */
-#define UDCCN(x) __REG2(0x40600400, (x)<<2)
+#define UDCCN(x) (0x40600400 + ((x) << 2))
#define UDCCRA 0x40600404 /* Configuration register EPA */
#define UDCCRB 0x40600408 /* Configuration register EPB */
#define UDCCRC 0x4060040C /* Configuration register EPC */
#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
#define UDC_BCR_MASK (0x3ff)
-#endif /* CONFIG_PXA27X */
+#endif /* CONFIG_CPU_PXA27X */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
/******************************************************************************/
/*
#define UHCHIE 0x4C000068
#define UHCHIT 0x4C00006C
+#define UHCCOMS_HCR (1<<0)
+
#define UHCHR_FSBIR (1<<0)
#define UHCHR_FHR (1<<1)
#define UHCHR_CGR (1<<2)
#define UP2OCR_CPVPE (1<<1)
#define UP2OCR_CPVEN (1<<0)
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
/******************************************************************************/
/*
#define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */
#define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */
#define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */
#define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */
#define OMCR10 0x40A000D8 /* OS Match Control Register 10 */
#define OMCR11 0x40A000DC /* OS Match Control Register 11 */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
#define OSSR_M4 (1 << 4) /* Match status channel 4 */
#define OSSR_M3 (1 << 3) /* Match status channel 3 */
#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#if !defined(CONFIG_PXA27X)
+#if !defined(CONFIG_CPU_PXA27X)
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
#endif
#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */
#endif
#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
-#if !defined(CONFIG_PXA27X)
+#if !defined(CONFIG_CPU_PXA27X)
#define CCCR_L09 (0x1F)
#define CCCR_L27 (0x1)
#define CCCR_L32 (0x2)
#define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */
#define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */
#define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */
#define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */
#define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */
#define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */
#define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
/*
* Interrupt Controller
#define ICPR 0x40D00010 /* Interrupt Controller Pending Register */
#define ICCR 0x40D00014 /* Interrupt Controller Control Register */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */
#define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */
#define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */
#define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */
#define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */
#define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
/******************************************************************************/
/*
#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */
#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */
#define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */
#define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */
#define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */
#define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */
#define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
#ifdef CONFIG_CPU_MONAHANS
#define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */
#define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3))
#define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2))
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
#define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
#define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
#define LCCR0_PDD_S 12
#define LCCR0_BM (1 << 20) /* Branch mask */
#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */
#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */
#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */
#define LCSR1_IU6 (1 << 29)
#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
#define LDCMD_SOFINT (1 << 22)
#define LDCMD_EOFINT (1 << 21)
#endif
#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
#define ARB_CNTRL 0x48000048 /* Arbiter Control Register */
#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
-#endif /* CONFIG_PXA27X */
+#endif /* CONFIG_CPU_PXA27X */
/* LCD registers */
#define LCCR4 0x44000010 /* LCD Controller Control Register 4 */
#define OSCR4 0x40A00040 /* OS Timer Counter Register */
#define OMCR4 0x40A000C0 /* */
-#endif /* CONFIG_PXA27X */
+#endif /* CONFIG_CPU_PXA27X */
#endif /* _PXA_REGS_H_ */
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