imx25: Add new hardware registers

[oweals/u-boot.git] / arch / arm / include / asm / arch-orion5x / orion5x.h

diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h
index 18225b9b49624fa144cfd15f81858fab8720dd2d..fbb1de8c0d993ba4d26a9f15b410e2a05b1f798a 100644 (file)
--- a/arch/arm/include/asm/arch-orion5x/orion5x.h
+++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
@@ -8,23 +8,7 @@
  *
  * Header file for Marvell's Orion SoC with Feroceon CPU core.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _ASM_ARCH_ORION5X_H
@@ -58,6 +42,18 @@
 #define MAX_MVGBE_DEVS 1
 #define MVGBE0_BASE    ORION5X_EGIGA_BASE
 
+/* Orion5x USB Host controller is port 1 */
+#define MVUSB0_BASE                    ORION5X_USB20_HOST_PORT_BASE
+#define MVUSB0_CPU_ATTR_DRAM_CS0       ORION5X_ATTR_DRAM_CS0
+#define MVUSB0_CPU_ATTR_DRAM_CS1       ORION5X_ATTR_DRAM_CS1
+#define MVUSB0_CPU_ATTR_DRAM_CS2       ORION5X_ATTR_DRAM_CS2
+#define MVUSB0_CPU_ATTR_DRAM_CS3       ORION5X_ATTR_DRAM_CS3
+
+/* Kirkwood CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA    ORION5X_CPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE       ORION5X_WIN_ENABLE
+#define MVCPU_WIN_DISABLE      ORION5X_WIN_DISABLE
+
 #define CONFIG_MAX_RAM_BANK_SIZE               (64*1024*1024)
 
 /* include here SoC variants. 5181, 5281, 6183 should go here when