board: ti: dra71x-evm: Add PMIC support

[oweals/u-boot.git] / arch / arm / include / asm / arch-omap5 / omap.h

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index cfec5b063c213b162663f57ccf6d041d134db1f5..b5e5519fbde54be62cd5c1fd5d8cef551a2859fc 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -16,6 +16,8 @@
 #include <asm/types.h>
 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
 
+#include <linux/sizes.h>
+
 /*
  * L4 Peripherals - L4 Wakeup and L4 Core now
  */
@@ -27,13 +29,13 @@
 #define CONTROL_CORE_ID_CODE   0x4A002204
 #define CONTROL_WKUP_ID_CODE   0x4AE0C204
 
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
 #define CONTROL_ID_CODE                CONTROL_WKUP_ID_CODE
 #else
 #define CONTROL_ID_CODE                CONTROL_CORE_ID_CODE
 #endif
 
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
 #define DRA7_USB_OTG_SS1_BASE          0x48890000
 #define DRA7_USB_OTG_SS1_GLUE_BASE     0x48880000
 #define DRA7_USB3_PHY1_PLL_CTRL                0x4A084C00
@@ -183,14 +185,16 @@ struct s32ktimer {
  * much larger) and do not, at this time, make use of the additional
  * space.
  */
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
 #define NON_SECURE_SRAM_START  0x40300000
 #define NON_SECURE_SRAM_END    0x40380000      /* Not inclusive */
+#define NON_SECURE_SRAM_IMG_END        0x4037E000
 #else
 #define NON_SECURE_SRAM_START  0x40300000
 #define NON_SECURE_SRAM_END    0x40320000      /* Not inclusive */
+#define NON_SECURE_SRAM_IMG_END        0x4031E000
 #endif
-#define SRAM_SCRATCH_SPACE_ADDR        0x4031E000
+#define SRAM_SCRATCH_SPACE_ADDR        (NON_SECURE_SRAM_IMG_END - SZ_1K)
 
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE     0x4031F000
@@ -216,6 +220,9 @@ struct s32ktimer {
 /* ABB tranxdone mask */
 #define OMAP_ABB_MPU_TXDONE_MASK               (0x1 << 7)
 #define OMAP_ABB_MM_TXDONE_MASK                        (0x1 << 31)
+#define OMAP_ABB_IVA_TXDONE_MASK               (0x1 << 30)
+#define OMAP_ABB_EVE_TXDONE_MASK               (0x1 << 29)
+#define OMAP_ABB_GPU_TXDONE_MASK               (0x1 << 28)
 
 /* ABB efuse masks */
 #define OMAP5_ABB_FUSE_VSET_MASK               (0x1F << 24)