Merge branch 'master' of git://git.denx.de/u-boot-mips

[oweals/u-boot.git] / arch / arm / include / asm / arch-omap5 / omap.h

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 27253929699e5cf8f37bfa300495c156a2faa43b..9dce49ac4b3a705be8c22b2c8c992b02c8651fd1 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -40,7 +40,7 @@
 #define OMAP54XX_L4_PER_BASE   0x48000000
 
 #define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
-#define OMAP54XX_DRAM_ADDR_SPACE_END   0xD0000000
+#define OMAP54XX_DRAM_ADDR_SPACE_END   0xFFFFFFFF
 #define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
 #define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
 
@@ -56,7 +56,8 @@
 #define CONTROL_ID_CODE                (CTRL_BASE + 0x204)
 
 /* To be verified */
-#define OMAP5_CONTROL_ID_CODE_ES1_0    0x0B85202F
+#define OMAP5430_CONTROL_ID_CODE_ES1_0         0x0B94202F
+#define OMAP5432_CONTROL_ID_CODE_ES1_0         0x0B99802F
 
 /* STD_FUSE_PROD_ID_1 */
 #define STD_FUSE_PROD_ID_1             (CTRL_BASE + 0x218)
@@ -98,17 +99,6 @@
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
 
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE               0x4AE06000
-#define PRM_DEVICE_BASE                (PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL            PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET      0x01
-
 /* Control Module */
 #define LDOSRAM_ACTMODE_VSET_IN_MASK   (0x1F << 5)
 #define LDOSRAM_VOLT_CTRL_OVERRIDE     0x0401040f
@@ -125,9 +115,10 @@
 /* CONTROL_EFUSE_2 */
 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1           0x00ffc000
 
-#define MMC1_PWRDNZ                                    (1 << 26)
-#define MMC1_PBIASLITE_PWRDNZ                          (1 << 22)
-#define MMC1_PBIASLITE_VMODE                           (1 << 21)
+#define SDCARD_PWRDNZ                                  (1 << 26)
+#define SDCARD_BIAS_HIZ_MODE                           (1 << 25)
+#define SDCARD_BIAS_PWRDNZ                             (1 << 22)
+#define SDCARD_PBIASLITE_VMODE                         (1 << 21)
 
 #ifndef __ASSEMBLY__
 
@@ -188,7 +179,14 @@ struct omap_sys_ctrl_regs {
        u32 control_srcomp_east_side; /*0x4A002E7C*/
        u32 control_srcomp_west_side; /*0x4A002E80*/
        u32 control_srcomp_code_latch; /*0x4A002E84*/
-       u32 pad4[3680198];
+       u32 pad4[3679394];
+       u32 control_port_emif1_sdram_config;            /*0x4AE0C110*/
+       u32 control_port_emif1_lpddr2_nvm_config;       /*0x4AE0C114*/
+       u32 control_port_emif2_sdram_config;            /*0x4AE0C118*/
+       u32 pad5[10];
+       u32 control_emif1_sdram_config_ext;             /* 0x4AE0C144 */
+       u32 control_emif2_sdram_config_ext;             /* 0x4AE0C148 */
+       u32 pad6[789];
        u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
        u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
        u32 control_padconf_mode; /* 0x4AE0CDA8 */
@@ -243,6 +241,12 @@ struct omap_sys_ctrl_regs {
 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
 
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL    0x7C7C7C6C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL       0x64646464
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE                         0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE                         0xBC6318DC
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE                         0x0
+
 #define EFUSE_1 0x45145100
 #define EFUSE_2 0x45145100
 #define EFUSE_3 0x45145100
@@ -258,8 +262,6 @@ struct omap_sys_ctrl_regs {
 #define NON_SECURE_SRAM_END    0x40320000      /* Not inclusive */
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE     0x4031F000
-/* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK   NON_SECURE_SRAM_END
 
 #define SRAM_SCRATCH_SPACE_ADDR                NON_SECURE_SRAM_START
 /*