bitops: collect BIT macros to include/linux/bitops.h

[oweals/u-boot.git] / arch / arm / include / asm / arch-omap5 / cpu.h

diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 6109b92777c9b8c184e553f2003c847af55a393b..26e741745920569d86b835f52120529f2806b5c3 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -18,6 +18,8 @@
 
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+#include <asm/ti-common/omap_wdt.h>
+
 struct gptimer {
        u32 tidr;               /* 0x00 r */
        u8 res1[0xc];
@@ -44,6 +46,7 @@ struct gptimer {
 /* enable sys_clk NO-prescale /1 */
 #define GPT_EN                 ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
 
+#define WDT_BASE                (OMAP54XX_L4_WKUP_BASE + 0x14000)
 /* Watchdog */
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
@@ -56,8 +59,6 @@ struct watchdog {
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
-#define BIT(x)                         (1 << (x))
-
 #define WD_UNLOCK1             0xAAAA
 #define WD_UNLOCK2             0x5555
 
@@ -118,4 +119,16 @@ struct watchdog {
 #define CPSW_BASE                      0x48484000
 #define CPSW_MDIO_BASE                 0x48485000
 
+/* gmii_sel register defines */
+#define GMII1_SEL_MII          0x0
+#define GMII1_SEL_RMII         0x1
+#define GMII1_SEL_RGMII                0x2
+#define GMII2_SEL_MII          (GMII1_SEL_MII << 4)
+#define GMII2_SEL_RMII         (GMII1_SEL_RMII << 4)
+#define GMII2_SEL_RGMII                (GMII1_SEL_RGMII << 4)
+
+#define MII_MODE_ENABLE                (GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE      (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+
 #endif /* _CPU_H */